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1.5 to 3 MHz frequency doubler circuit
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Gandalf_Sr:
The cost difference between an Op Amp and a D-Type flip flop is unimportant but the flip flop (say a 74HC174) has a 13 nS delay which is significant given the periodic time for the 3.072 MHz output is 325.5 nS. Maybe the Op Amp is the way to go? Or can I realize the divide by 2 using a faster logic family? Remember that my supply voltage is 3.3V.

[Cruise update] Docked in Ushuaia with perfect weather - we went around Cape Horn yesterday in near millpond like conditions.
edavid:

--- Quote from: Gandalf_Sr on December 31, 2018, 09:50:23 am ---The cost difference between an Op Amp and a D-Type flip flop is unimportant but the flip flop (say a 74HC174) has a 13 nS delay which is significant given the periodic time for the 3.072 MHz output is 325.5 nS. Maybe the Op Amp is the way to go? Or can I realize the divide by 2 using a faster logic family? Remember that my supply voltage is 3.3V.

--- End quote ---

You are mixing up 2 different red herrings:

1. The op amp would be part of a PLL active loop filter, which you wouldn't need.

2. The divider flip flop (74HC74, not 174) propagation delay would be removed by the action of the PLL.  The offset between the two clocks is determined by the phase detector characteristics.
Benta:
I have to agree with edavid.
The flipflop or divider delay in the PLL would rather advance the output of the VCO, so the VCO output will lead the input. This can easily be compensated, but still...

The RC delay plus XOR is still the best solution for a simple constant frequency doubling IMO.

Gandalf_Sr:

--- Quote from: edavid on December 31, 2018, 05:16:24 pm ---...The divider flip flop (74HC74, not 174) propagation delay would be removed by the action of the PLL.  The offset between the two clocks is determined by the phase detector characteristics.

--- End quote ---
If the phase comparator compares the original 1.536 MHz clock input to the VCO output fed through a /2 flip fop that introduces a 13 nS delay then surely the output signal edges will lead the edges of the input signal by 13 nS?

I agree that the XOR should work but it doesn't, at least not reliably.  I have a thread running on this on TI's e2e forum - the question is why the TAS5755M doesn't like my slightly jittery and variable M/S ratio doubled MCLK, maybe they'll shed some light on this eventually?  Perhaps the fact that the SCLK and associated signals come on before the MCLK does is something the Amp doesn't like?

Thanks for the proactive input folks, and a Happy New Year to you all.
spec:
Just a suggestion, but wouln't the SN74LV4046A PLL chip be worth considering. It is high performance and 3V3 compatible.

http://www.ti.com/lit/ds/symlink/sn74lv4046a.pdf
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