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| 1.5 to 3 MHz frequency doubler circuit |
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| spec:
(3MHz = 3.072 MHz and 1.5MHz = 1.536 MHz throughout) This is an intriguing thread, because the requirement is a lot more demanding than would first appear. The suggested solutions so far (hope I have this right) are: * XOR with open loop mark to space ratio (MSR) definition * PLL * TransformerI have been looking at other approaches as well: * logic frequency doubling (similar to XOR above) with two analog servo control loops to provide an accurate 1:1 mark to space ratio of the 3MHz signal (LDAS) * Digital Sampling Counter (DSC)The LDAS approach is reasonably self explanatory, so I will only describe the DSC approach: The inputs to the DSC are the 1.5 MHz reference signal, and a clock reference signal (CRS) of as high a frequency as the logic in use will take, say 100mHz, for the SN74LVxA family of logic chips running at a 3V3 supply line. The CRS absolute frequency is unimportant. The only requirement is that it is frequency stable for around 10uS and jitter free. A synchronous digital counter (DC1), clocked by CRS, counts the number of CRS periods in one cycle of the 1.5Mhz signal and loads 1/4 of the digital value into another synchronous digital counter (DC2) which is also clocked by CRS. The output of DC2 would then be a 3MHz signal with a 1:1 MSR, synced to the 1.5MHz reference signal. The only drift would be due to any drift of CRS over a 10uS period. Of course, if you really wanted to do a Rolls Royce job you could use ECL or PECL to get the sampling rate right up. The design of the DSC would be pretty straight forward for a digital designer and the physical the same. I recon the DSC could be implemented with four chips and possibly a 100mHz Xtal oscillator, but I haven't done a trial schematic. This is really thinking aloud but I would be interested to hear the general view of these two approaches, especially the DSC approach. |
| edavid:
--- Quote from: Gandalf_Sr on January 01, 2019, 11:05:34 am ---I agree that the XOR should work but it doesn't, at least not reliably. I have a thread running on this on TI's e2e forum - the question is why the TAS5755M doesn't like my slightly jittery and variable M/S ratio doubled MCLK, maybe they'll shed some light on this eventually? Perhaps the fact that the SCLK and associated signals come on before the MCLK does is something the Amp doesn't like? --- End quote --- We are talking about using an XOR phase detector for a PLL doubler, *not* about an XOR frequency doubler. |
| edavid:
--- Quote from: spec on January 01, 2019, 12:29:12 pm ---This is really thinking aloud but I would be interested to hear the general view of these two approaches, especially the DSC approach. --- End quote --- This is more commonly called a Frequency Locked Loop. It has its applications, but for a fixed frequency multiplier it has more jitter than the simpler open loop or PLL approaches, so it's not a good idea. |
| spec:
--- Quote from: edavid on January 01, 2019, 04:10:00 pm --- --- Quote from: spec on January 01, 2019, 12:29:12 pm ---This is really thinking aloud but I would be interested to hear the general view of these two approaches, especially the DSC approach. --- End quote --- This is more commonly called a Frequency Locked Loop. It has its applications, but for a fixed frequency multiplier it has more jitter than the simpler open loop or PLL approaches, so it's not a good idea. --- End quote --- Yes, I was wondering about the jitter. Thanks for the info :) |
| Benta:
--- Quote from: edavid on January 01, 2019, 04:08:08 pm --- --- Quote from: Gandalf_Sr on January 01, 2019, 11:05:34 am ---I agree that the XOR should work but it doesn't, at least not reliably. I have a thread running on this on TI's e2e forum - the question is why the TAS5755M doesn't like my slightly jittery and variable M/S ratio doubled MCLK, maybe they'll shed some light on this eventually? Perhaps the fact that the SCLK and associated signals come on before the MCLK does is something the Amp doesn't like? --- End quote --- We are talking about using an XOR phase detector for a PLL doubler, *not* about an XOR frequency doubler. --- End quote --- Problem is, that the simple XOR phase/frequency detector does not have phase coherence. It can be anywhere between -90 and +90 degrees. |
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