| Electronics > Projects, Designs, and Technical Stuff |
| 1.5 to 3 MHz frequency doubler circuit |
| (1/10) > >> |
| Gandalf_Sr:
I have a design where a Cypress BLE module feeds I2S audio data to a TAS5755M TI Amplifier. The problem is that the Amp needs an extra clock signal called MCLK of 3.072 MHz and it needs to be a doubled, synched multiple the I2S SCLK signal of 1.536 MHz. I built a circuit like this... https://www.maximintegrated.com/en/app-notes/index.mvp/id/3327 But there's a lot of jitter and variations on the mark-space ratio on the output so it's very unreliable and only works occasionally. I thought it would be simple to build a PLL circuit set up as a doubler with 1.536MHz in and 3.072 MHz out but all the ICs I've looked at have a minimum output frequency that's too low (I looked at the 74HC4046a and the PT7C4511). Can anyone here suggest an IC or circuit that will meet my needs? My operating voltage is 3.3V. Thanks in advance. |
| jpb:
I'm not a great expert but I thought the 4046 was happy producing kHz. The example in "The Art of Electronics" is using it go go from 60Hz to 61.44 kHz. So I'm surprised it can't do 3.072 MHz as being "too low". |
| Gandalf_Sr:
Thanks for the suggestion. Maybe there's a 4046 family member that will work but the CD4046B won't run properly at 3.3V and the max Fout is <3 MHz. The 74HC4046A has a min VCO Fcenter of 12MHz - this is all from memory over my recent research so I may have made mistakes. I'm at sea on a cruise in the S Atlantic and the Internet is a bit slow. |
| soldar:
--- Quote from: Gandalf_Sr on December 27, 2018, 02:00:04 pm ---But there's a lot of jitter and variations on the mark-space ratio on the output so it's very unreliable and only works occasionally. --- End quote --- That circuit should work. Is the power supply to the comparator absolutely stable and filtered? If the input is a nicely cut rectangular signal then jitter should not be an issue and the circuit, should not have much jitter. The duty cycle issue is different. The easiest way to have a 50% duty cycle is to start with double the frequency and then divide by two. |
| Gandalf_Sr:
I stuck with having to double as I can't get to the 3.072 MHz signal that presumably exists inside the Cypress BLE module (I asked). I just posted in TI's e2e forum although it only went through on my 4th try - I have problems with that forum even when I'm on a light-speed connection, doing it over the ship's zoom satellite connection is almost impossible. |
| Navigation |
| Message Index |
| Next page |