100k, 1mhz clock divider to 60.0000hz?

[Old Goat]

Well, search as I might, I've not run into a clock divider which seems suitable for a purpose I have in mind. What I want is a gadget to divide my GPS receiver's output (I have a choice of 100k, 1mhz, 5 mhz, 10mhz, etc) to 60.000hz. The purpose being to provide a clock signal to a free-running display which I have on my bench. Just for local time of day, nothing more important than that. Any suggestions here about a hardware solution which might be "plug in and go", or (second choice) perhaps a circuit which I could put together in an afternoon? I'm quite sure that there are software solutions, but that would probably be far more complex than I want to mess with. Ideas? Thanks, all, in advance.

Edit: Thank you all for your ideas and suggestions. Some I'd not considered.

So, let me correct my original statement slightly - the clock display is a single IC clock chip driven by the 60hz main supply here in the US, but does indeed drift as compared to my two GPS receivers. One is a TrueTime (which has the jumper selectable output clocks frequencies), and the other is a Trimble which I placed in a rackmount chassis also. I use these as master clocks for frequency counters, etc. Now, I've not actually checked carefully the apparent drift over a period of days, I just notice that it's off by several seconds to maybe a minute or so when I do check occasionally (every few days, or a week or so).

The real nuisance part of this story is that TrueTime makes a display which is driven from IRIG-B, which my TrueTime receiver outputs as well as the selectable 100k, 1m, clocks etc. I had one a few years before I purchased the TrueTime GPS receiver, but I sold it because I didn't think I'd ever use it.

So there is where I am, and it's just a matter of curiosity, not necessity that I would like a display on the bench that remains "on time", day to day.

So, again, thank you, and keep the ideas coming.

[Kim Christensen]

provide a clock signal to a free-running display which I have on my bench

Since it is running on the bench in the USA, why not power it from AC and use the line frequency as your reference?

Or, if you really want to use the GPS, you can periodically sync it with the GPS by reading the NEMA sentence if your GPS outputs one. (This requires a microcontroller of some kind.)

[Alex Eisenhut]

That's a pretty specific requirement.

https://www.eevblog.com/forum/projects/is-there-a-60hz-oscillator/

[Leo Bodnar]

Use a PIC16 or PIC18, drive it directly from 10MHz and every 20833 instruction cycles toggle an output pin.
After every three toggles add another instruction as a delay.

10MHz / 4 = 2.5MIPS = 20833.3 half-cycles of 60Hz

Leo

[MarkF]

you could use a combination of binary and decade counters to do the division plus a few logic gates set the proper count (i.e. do a count reset).  Will take at least 4 counters for your lowest 100K GPS output.

SN54LS160A THRU SN54LS163A SYNCHRONOUS 4-BIT COUNTERS

[jpanhalt]

I'm quite sure that there are software solutions, but that would probably be far more complex than I want to mess with. Ideas? Thanks, all, in advance.

Code is available that will give "0%" error, if you clock an MCU with it.  See here: https://www.golovchenko.org/home/delay_loops 
 Very little complexity.

EDIT: I am getting a 404 with that link, but from his home page it works.  Maybe something at my ISP.
EDIT2: Thanks for the clue.  I didn't check what the post here interpreted from a cut and paste.  Fixed.

[Benta]

60 Hz is problematic, as there is no integer relationship to 100 kHz or 1 MHz.
You need a "Dual Modulo" counter, meaning it will divide by N and N+1. On each output cycle you'll have a period that's slightly low or high, but over a few cycles (in this case three) will be 100% correct.
The question is how much jitter you can tolerate on your 60 Hz output?
Examples:

100 kHz input:
Divide ratios: 1667, 1667, 1666, 1667, 1667, 1666, 1667 ... 10 us jitter on the 60 Hz output.

1 MHz input:
Divide ratios: 16667, 16667, 16666, 16667, 16667, 16666 ... 1 us jitter.

A normal programmable counter chain (eg, 74HC161) will do the trick.
Let the output of the counter clock a 0...2 counter (two FFs and a few gates suffice) that controls N or N+1 behaviour of the main counter. This is done by setting the LSB of the main counter programming input high or low.

[I wanted a rude username]

Code is available that will give "0%" error, if you clock an MCU with it.  See here: https://www.golovchenko.org/home/delay_loops.  Very little complexity.

EDIT: I am getting a 404 with that link, but from his home page it works.  Maybe something at my ISP.

Simpe Machines Forum included the period in its automatic wrapping of the URL into a hyperlink. It works without the period: https://www.golovchenko.org/home/delay_loops

This is a good resource for common cases, but would need to be modified to perform the one-in-three correction that Leo suggested. Generated code:

Code: [Select]

; Delay = 0.00833333 seconds
; Clock frequency = 1 MHz

; Actual delay = 0.008332 seconds = 2083 cycles
; Error = 0.016 %

cblock
d1
d2
endc

;2083 cycles
movlw 0xA0
movwf d1
movlw 0x02
movwf d2
Delay_0
decfsz d1, f
goto $+2
decfsz d2, f
goto Delay_0

[edavid]

If you don't want to do any programming, it would be easy to multiply 100KHz by 3 with a CD4046 or 74HC4046 + 74HC163, then divide by 5000 with 2 74HC390s.

[ve7xen]

Why 60Hz? Is this a hard requirement of the existing 'free-running display', or are you free to modify this device as well? If the 'free-running display' supports 50Hz 'mains' as well, this would be much easier as it has an integer relationship to your available clock frequencies, so the divider would be trivial and low jitter. Choose the lowest available clock frequency (100khz) and divide by 2000 using 74 series logic (e.g. 74HC4040).

Or for a single-chip solution, use the PWM peripheral or cycle-counted delay loops in any typical microcontroller to do the same.

You may also consider using a u-blox GPS (or maybe others that have this feature), then you can just configure your desired output frequency directly from the receiver, and it will be fairly low jitter even if it's a non-integer fraction, because it will be clocked directly from the receiver's timebase. You can get a NEO-6M module (or clone) for < $5 on eBay that can do this. Just make sure the board includes an EEPROM (most do), so you can store the nonstandard timepulse configuration.

[amyk]

Perhaps a PLL might be usable?

[bingo600]

A cheap - STM32F030F4P6 board might do it , using the built in PLL
https://www.ebay.com/itm/254239322313

If you feed the HSE clock w. 10MHz , and set the PLL clock parms to Divide by 5 , and MUL by 12 , you'll get a 24MHz PLL Clock.
If you then set the timer prescaler to ie. 1000 , then you'd match on 400 (200 for a 60Hz clock gen) , keeping it nicely within a 16bit timer.

You might have a bit of jitter , but if it's for clock ticks .. I don't think it would matter.

I'm not a stm32 guru yet , but that's prob. the i'd give a try.

Well i'd prob get a F401 "Black pill" , and use a 96MHz PLL clock (matches on 1600/800) ...
Just because it is easier to use the stm32duino firmware , and  load the firmware directly via usb ,  It also has 32bit timers
https://www.ebay.com/itm/184549449179


But the F030 Xtal is easier to remove

A "BluePill" at 84MHz would also do it (1400/700) , if you have one "in the drawer"

[BrianHG]

Well, search as I might, I've not run into a clock divider which seems suitable for a purpose I have in mind. What I want is a gadget to divide my GPS receiver's output (I have a choice of 100k, 1mhz, 5 mhz, 10mhz, etc) to 60.000hz. The purpose being to provide a clock signal to a free-running display which I have on my bench.

He does not need jitter free, just a perfect dividing 10mhz into 60hz.

I would just make a PIC program which took in the 10MHz.  Internally generate a perfect 10Hz interrupt using the internal own capture compare counter set to divide the system clock by 1000000/4/250000=10hz.

I would then just loop-toggle an IO close to 60hz with nothing more than a software delay loop while the PWM interrupt will be used to reset that generator of 6 pulses.  At then end of every 6th output cycle, the next cycle will begin early or late by a few 100s of nanoseconds as it waits for that PWM interrupt timer to begin again.

Perfect for a 60hz compatible clock for display.

Also any cheap bottom end CPLD/FPGA can also do this with ease.

[Old Goat]

If you don't want to do any programming, it would be easy to multiply 100KHz by 3 with a CD4046 or 74HC4046 + 74HC163, then divide by 5000 with 2 74HC390s.

 I like this idea, and I'll pursue it. I like it as it appears to be relatively "quick and easy" to implement.

 It was also mentioned that if the clock were able to utilize 50 hz, that might make the solution even easier. I had not considered this possibility, so will take a look at the clock IC and see if that's an option.

Thank all of you, keep 'em coming!

[EPAIII]

There are dedicated counter chips that can be hard wired to count to any number and then reset. But 60 has the factor of 3 in it and none of the available numbers you list are evenly divisible by 3 so no single count is going to do it. For instance, for your 10 MHz source you would need to divide by 166,666.6666666...

What you do need to do is use software to count to one number two time and then to a second number the third time. This will be off by a very small factor on each count, but will average out to exact every three counts. For a time of day clock it should be just fine.

For 10 MHz you would count to 166,667 two times and then to 166,666 once. And then repeat that cycle.

But there is another, easier way to get the correct time of day. At Walmart I purchased a Westclock, "Atomic Clock" which synchronizes with the WWV transmissions. These transmissions are used by serious users such as labs and others who want the correct time. You can even get correction figures they publish when extreme accuracy is needed for corrections to observations after the fact. So they are traceable to the US standard time as maintained by THE actual atomic clocks by NIST.

https://en.wikipedia.org/wiki/WWV_(radio_station)

This is the widely used standard for time of day in the US and other countries as well. I looked and Walmart no longer has that exact clock, but there are at least two others on their web site that are labeled "atomic clock". I believe I only paid about $25 at the time and I see others that are available for less today.

The beauty of these "atomic clocks" is they will automatically synchronize with the nearest WWV station within a few minutes, certainly at the top of the hour, after a power loss or battery change. So they are self setting. Mine is battery powered, just sits behind my desk and always has the correct time. I really need to buy more for around the house.

[MarkF]

Can no one count in this topic?   

Here's a quick circuit that may not be exactly correct.
Basically, you reset the counter when it reaches 60.

A MCU with a 32.768MHz oscillator would be the best way to go.  It would save many chips.

 

[Benta]

Can no one count in this topic?   

Congratulations on misunderstanding the issue 100%. Dividing by 60 is no problem, everyone knows how to do that. 

And by the way, your design is not good. The purpose of the 74161 is programming it. Using the /MR is amateurish.

[Benta]

This circuit will do a 1666.66666.... division.
Meaning 100 kHz -> 60 Hz (but with 10 us jitter).

But with the ridiculous prices of 74HC nowadays, I don't know. In normal times it would cost less than 50 cents.

[Old Goat]

This circuit will do a 1666.66666.... division.
Meaning 100 kHz -> 60 Hz (but with 10 us jitter).

But with the ridiculous prices of 74HC nowadays, I don't know. In normal times it would cost less than 50 cents.

This is quite what I had in mind, what I thought was possible, but didn't know how to go about it myself.

I have two questions though. 1) why are the J/K outputs of IC5B tied together? and 2) are the inputs to the  74HC161 counters tied "hi" and "low" via maybe 10k resistors? Is that what is meant by the "1" and "0" annotations?

Thank you for this.

And to the reply which suggested an "atomic" clock, I had considered this, but my purpose isn't serious enough to warrant another clock in the shop, this is mostly an issue of 'can I do it', and if so, how? Thank you again to all who responded.

The Old Goat

[Terry Bites]

Keep it simple
A standard 18.432 MHz div1024 div5
or much more fun:
An ELM440 with an NTSC Xtal. $10 should cover it.

[SiliconWizard]

Keep it simple
A standard 18.432 MHz div1024 div5
or much more fun:
An ELM440 with an NTSC Xtal. $10 should cover it.

But the OP explicitely wanted to use the clock reference from a GPS receiver.

[Benta]

This is quite what I had in mind, what I thought was possible, but didn't know how to go about it myself.

I have two questions though. 1) why are the J/K outputs of IC5B tied together? and 2) are the inputs to the  74HC161 counters tied "hi" and "low" via maybe 10k resistors? Is that what is meant by the "1" and "0" annotations?

1: J/K are inputs. And you're right, there's an error in the schematic there. The K input of IC5B should be tied to '1', which leads to your next question.
2: '0' and '1' are VDD and VEE. With 74HC logic you can safely tie inputs directly to the supply rails, no need for resistors.

Just to explain the circuit better: the HC161/163 counter chain is a normal 12-bit programmable counter.
Computing the programming pattern from the division ratio N is done by using 2^12 - N or 4096 - N.
In this case 4096 - 1666 and 4096 - 1667, giving 2430 and 2429. The counter is hardwired to a divide ratio of 2428, the two LSBs are added by the FFs (01 and 10).
The two JK FFs are a divide-by-three counter, programming the main counter with 2430, 2429 and 2429 (not necessarily in that order).
Hope this is clear.

EDIT: I've modified the schematic in Reply #17. It should be OK now. The /R inputs to U5 should be tied high, of course. I was too lazy to add that I'll admit.

[NiHaoMike]

Does the GPS receiver have a "PPS" output? I'm thinking the easiest solution might be a RC oscillator set to run at about 70Hz (not critical, just has be be above 60Hz) gated by a flip flop that starts it when a PPS pulse is received and stops it when it detects the second tick over from the clock. Could possibly be done with a single CMOS logic chip or a 556.

[Benta]

Does the GPS receiver have a "PPS" output? I'm thinking the easiest solution might be a RC oscillator set to run at about 70Hz (not critical, just has be be above 60Hz) gated by a flip flop that starts it when a PPS pulse is received and stops it when it detects the second tick over from the clock. Could possibly be done with a single CMOS logic chip or a 556.

It's an idea. But I would worry a bit about "hit and miss" situations where the cut off from the FF would create pulses so narrow that a decision between 0 and 1 gets difficult.

[spostma]

I would use a 6-pin or 8-pin PIC with 20-bit NCO like the PIC16F15313-I/P

The NCO F_OVERFLOW = NCO_Clock_Frequency * IncrementValue / 2²⁰
which allows rougly a one per million divisor resolution.

The NCO output signal can be output immediately to a pin,
or used in the 4-macrocell CLC if needed.

The only firmware needed is to set up the NCO unit, the rest is done in hardware.
I think that the easiest compiler for this would be GreatCowBasic,:
https://sourceforge.net/projects/gcbasic/