Hi
I am designing an RTM board for an ATCA crate. The rtm is for a Trigger Processor carrier board that has a couple 7 series Xilinx FPGA's with GTY transceivers that will be sending and receiving data through a fancy new EBTF samtec high density high speed zone3 connector. My RTM has 8 QSFP modules that will have a total of 31 channels that have to run 10Gbps. I am curious if there is anyone on the forum that has experience designing multi gigbit designs. Our first prototype was a flop and my BER is 10^-10 and 10^-9

when I run Xilinix's IBERT project using a PRBS31 but works some what at PRBS7.
Cheers