Well the obvious lineup is a Schmidt trigger to guarantee consistent fast input transitions, an XOR edge detector and a retriggerable monostable for the output pulse, with a variable timing resistor, all in 4000 series CMOS logic. Even if you cheat and use a quad XOR with two of its gates strapped as non-inverting buffers with positive feedback to make them Schmidt triggers for the input and delay path, that's still two ICs.
I think you can do it with a single 4106 hex Schmitt inverter used creatively. One gate to square up the input, then AC couple it with a short time constant to get a bi-polarity pulse from both edges, eliminate the negative going half, and square it up with another gate, leaving several gates to implement the monostable. It *MAY* need a transistor to discharge the timing cap faster than a 4000 CMOS output can manage.