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16 bit to 4 digit 7 segment decoder
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Benta:
To generate the 4-bit to 7-segment decoding, the simplest solution is simply a 16 x 8 array. Each byte is the segment assignments, and is addressed by the 4-bit input. This should be simple to implement in a CPLD.

oPossum:

--- Quote from: obiwanjacobi on December 20, 2019, 04:15:57 pm ---Have not taken the time to analyze what went wrong here...

--- End quote ---

I think the difference is that the VHDL equations determine when a segment should be off rather than on.

Here is annotated equations that make this clearer...

--- Code: ---seg_a_out     = !(  !hex_in_a_3_ & !hex_in_a_2_ & !hex_in_a_1_ &  hex_in_a_0_   0001 1
                 #  !hex_in_a_3_ &  hex_in_a_2_ & !hex_in_a_1_ & !hex_in_a_0_   0100 4
                 #   hex_in_a_3_ & !hex_in_a_2_ &  hex_in_a_1_ &  hex_in_a_0_   1011 B
                 #   hex_in_a_3_ &  hex_in_a_2_ & !hex_in_a_1_ &  hex_in_a_0_)  1101 D

seg_b_out     = !(  !hex_in_a_3_ &  hex_in_a_2_ & !hex_in_a_1_ &  hex_in_a_0_   0101 5
                 #                  hex_in_a_2_ &  hex_in_a_1_ & !hex_in_a_0_   X110 6 E
                 #   hex_in_a_3_ &                 hex_in_a_1_ &  hex_in_a_0_   1X11 B F
                 #   hex_in_a_3_ &  hex_in_a_2_ &                !hex_in_a_0_)  11X0 C E

seg_c_out     = !(  !hex_in_a_3_ & !hex_in_a_2_ &  hex_in_a_1_ & !hex_in_a_0_   0010 2
                 #   hex_in_a_3_ &  hex_in_a_2_ &                !hex_in_a_0_   11X0 C E
                 #   hex_in_a_3_ &  hex_in_a_2_ &  hex_in_a_1_               )  111X E F

seg_d_out     = !(  !hex_in_a_3_ &  hex_in_a_2_ & !hex_in_a_1_ & !hex_in_a_0_   0100 4
                 #                 !hex_in_a_2_ & !hex_in_a_1_ &  hex_in_a_0_   X001 1 9
                 #                  hex_in_a_2_ &  hex_in_a_1_ &  hex_in_a_0_   X111 7 F
                 #   hex_in_a_3_ & !hex_in_a_2_ &  hex_in_a_1_ & !hex_in_a_0_)  1010 A

seg_e_out     = !(  !hex_in_a_3_ &                                hex_in_a_0_   0XX1 1 3 5 7
                 #                 !hex_in_a_2_ & !hex_in_a_1_ &  hex_in_a_0_   X001 1 9
                 #  !hex_in_a_3_ &  hex_in_a_2_ & !hex_in_a_1_               )  010X 4 5

seg_f_out     = !(  !hex_in_a_3_ & !hex_in_a_2_ &                 hex_in_a_0_   00X1 1 3
                 #  !hex_in_a_3_ & !hex_in_a_2_ &  hex_in_a_1_                  001X 2 3
                 #  !hex_in_a_3_ &                 hex_in_a_1_ &  hex_in_a_0_   0X11 3 7
                 #   hex_in_a_3_ &  hex_in_a_2_ & !hex_in_a_1_ &  hex_in_a_0_)  1101 D

seg_g_out     = !(  !hex_in_a_3_ & !hex_in_a_2_ & !hex_in_a_1_                  000X 0 1
                 #  !hex_in_a_3_ &  hex_in_a_2_ &  hex_in_a_1_ &  hex_in_a_0_   0111 7
                 #   hex_in_a_3_ &  hex_in_a_2_ & !hex_in_a_1_ & !hex_in_a_0_)  1100 C

--- End code ---
obiwanjacobi:
Yeah, your code is totally understandable. I initially removed all the inverts (!) of the output assignments because I thought you may have needed outputs to go low to activate. When I saw the result and took another closer look at the equations it became clear pretty quick.

I did not analyse my first version equations...


--- Quote from: Benta on December 20, 2019, 05:39:37 pm ---To generate the 4-bit to 7-segment decoding, the simplest solution is simply a 16 x 8 array. Each byte is the segment assignments, and is addressed by the 4-bit input. This should be simple to implement in a CPLD.

--- End quote ---

Times 4 digits and add multiplexing for the common cathode display module...
Benta:

--- Quote from: obiwanjacobi on December 20, 2019, 07:25:20 pm ---

--- Quote from: Benta on December 20, 2019, 05:39:37 pm ---To generate the 4-bit to 7-segment decoding, the simplest solution is simply a 16 x 8 array. Each byte is the segment assignments, and is addressed by the 4-bit input. This should be simple to implement in a CPLD.

--- End quote ---

Times 4 digits and add multiplexing for the common cathode display module...

--- End quote ---

No! You still don't understand. You only need to do the 4 -> 7 once. The multiplexing is done before the segment decoding.

16 bits ->  split to 4 x 4 bits. A 4-bit section (eg, digit #0) is fed to the 4 -> 7 decoder and from there to the display anodes. At the same time digit #0 (the common cathode) is selected. Repeat through digits #0...#3

Got it?

obiwanjacobi:
I think I got it. And that is what we've been talking about all along...?  :-//

If you take a look at my code for the 2 digit decoder I try to select the set of 4 bits to go into the 4-bit to 7-seg decoder TABLE based on the FF state (is digit #1 or digit #2 active?)

That is what you are saying is it not? Feed each set of 4-bits (out of the 16 bits total) into the decoder to get the correct segment outputs. In addition to that I also need to active-low the common cathode digit pin for the digit we're currently decoding...
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