Electronics > Projects, Designs, and Technical Stuff
16 bit to 4 digit 7 segment decoder
jmelson:
--- Quote from: obiwanjacobi on December 19, 2019, 10:48:13 am ---
Meantime I remembered 5V cpld's like the Xilinx XC9572XL. Not too expensive and should be a one chip solution...
--- End quote ---
The obsolete 9500 series is 5V power and signals. The 9500XL series is 3.3 V power, and TTL-compatible logic levels, 5V
tolerant. (Just to set the record straight.)
Jon
obiwanjacobi:
--- Quote from: jmelson on December 20, 2019, 08:10:54 pm ---
--- Quote from: obiwanjacobi on December 19, 2019, 10:48:13 am ---
Meantime I remembered 5V cpld's like the Xilinx XC9572XL. Not too expensive and should be a one chip solution...
--- End quote ---
The obsolete 9500 series is 5V power and signals. The 9500XL series is 3.3 V power, and TTL-compatible logic levels, 5V
tolerant. (Just to set the record straight.)
Jon
--- End quote ---
Yes thank you. I did notice that when I opened up the datasheet. It does have 5V tolerant pins but its supply is max 4V. That's when I realized...
Benta:
This is what I'm talking about. Super simple to implement in a CPLD.
"D" is digit = common cathode, "S" = segments
"A" and "B" are binary inputs from a 2-bit counter/oscillator.
oPossum:
Some VHDL for 4 digit 16 bit muxed. Fits in a Lattice LSI1016.
--- Code: ---entity hex_decode_16 is
port(
clk: in std_logic;
reset: in std_logic;
hex_in_a: in std_logic_vector ( 3 downto 0 );
hex_in_b: in std_logic_vector ( 3 downto 0 );
hex_in_c: in std_logic_vector ( 3 downto 0 );
hex_in_d: in std_logic_vector ( 3 downto 0 );
seg_a_out: out std_logic;
seg_b_out: out std_logic;
seg_c_out: out std_logic;
seg_d_out: out std_logic;
seg_e_out: out std_logic;
seg_f_out: out std_logic;
seg_g_out: out std_logic;
dig_1_out: out std_logic;
dig_2_out: out std_logic;
dig_3_out: out std_logic;
dig_4_out: out std_logic);
end;
architecture Hex_decode_16 of hex_decode_16 is
signal digit: std_logic_vector(3 downto 0);
signal hex_in: std_logic_vector(3 downto 0);
signal segments: std_logic_vector (6 downto 0);
begin
process (clk, reset, hex_in_a, hex_in_b, hex_in_c, hex_in_d)
begin
if rising_edge(clk) then
if reset = '0' then
digit <= "0001";
else
digit <= digit(2) & digit(1) & digit(0) & digit(3);
end if;
end if;
case digit is
when "0001" => hex_in <= hex_in_a;
when "0010" => hex_in <= hex_in_b;
when "0100" => hex_in <= hex_in_c;
when "1000" => hex_in <= hex_in_d;
when others => hex_in <= "0000";
end case;
case hex_in is
when "0000" => segments <= "1111110";
when "0001" => segments <= "0110000";
when "0010" => segments <= "1101101";
when "0011" => segments <= "1111001";
when "0100" => segments <= "0110011";
when "0101" => segments <= "1011011";
when "0110" => segments <= "1011111";
when "0111" => segments <= "1110000";
when "1000" => segments <= "1111111";
when "1001" => segments <= "1110011";
when "1010" => segments <= "1110111";
when "1011" => segments <= "0011111";
when "1100" => segments <= "1001110";
when "1101" => segments <= "0111101";
when "1110" => segments <= "1001111";
when "1111" => segments <= "1000111";
end case;
(seg_a_out, seg_b_out, seg_c_out, seg_d_out, seg_e_out, seg_f_out, seg_g_out) <= segments;
(dig_4_out, dig_3_out, dig_2_out, dig_1_out) <= digit;
end process;
end Hex_decode_16;
--- End code ---
oPossum:
--- Quote from: obiwanjacobi on December 20, 2019, 12:00:41 pm ---Yes, I would need to use the OE of the GALs. But I would like to program the multiplexer FF inside GAL/GALs as well. Then you'll end up with almost two identical GALs... I would use an extra input to sync up the second GAL with the first (have a couple of free inputs).
--- End quote ---
I wanted to put the counter in the GAL but couldn't think of a way to do it and also have digit select outputs. There just weren't enough pins. After thinking about it some more I came up with this...
Master
--- Code: ---entity hex_decode_master is
port(
clk: in std_logic;
hex_in_a: in std_logic_vector ( 3 downto 0 );
hex_in_b: in std_logic_vector ( 3 downto 0 );
seg_a_out: out std_logic;
seg_b_out: out std_logic;
seg_c_out: out std_logic;
seg_d_out: out std_logic;
seg_e_out: out std_logic;
seg_f_out: out std_logic;
seg_g_out: out std_logic;
dig_c0_out: out std_logic;
dig_c1_out: out std_logic;
dig_0_out: out std_logic);
attribute LOC: string;
attribute LOC of clk: signal is "1";
attribute LOC of hex_in_a: signal is "5 4 3 2";
attribute LOC of hex_in_b: signal is "9 8 7 6";
-- 10
-- 11
-- Gnd 12
-- 13
attribute LOC of dig_0_out: signal is "14";
attribute LOC of dig_c0_out: signal is "15";
attribute LOC of seg_a_out: signal is "16";
attribute LOC of seg_b_out: signal is "17";
attribute LOC of seg_c_out: signal is "18";
attribute LOC of seg_d_out: signal is "19";
attribute LOC of seg_e_out: signal is "20";
attribute LOC of seg_f_out: signal is "21";
attribute LOC of seg_g_out: signal is "22";
attribute LOC of dig_c1_out: signal is "23";
-- Vcc 24
end;
architecture Hex_decode_master of hex_decode_master is
signal digit: std_logic_vector(1 downto 0);
signal hex_in: std_logic_vector(3 downto 0);
signal segments: std_logic_vector (6 downto 0);
begin
process (clk, hex_in_a, hex_in_b)
begin
if rising_edge(clk) then
digit <= digit + 1;
end if;
if digit(0) = '0' then
hex_in <= hex_in_a;
else
hex_in <= hex_in_b;
end if;
case hex_in is
when "0000" => segments <= "1111110";
when "0001" => segments <= "0110000";
when "0010" => segments <= "1101101";
when "0011" => segments <= "1111001";
when "0100" => segments <= "0110011";
when "0101" => segments <= "1011011";
when "0110" => segments <= "1011111";
when "0111" => segments <= "1110000";
when "1000" => segments <= "1111111";
when "1001" => segments <= "1110011";
when "1010" => segments <= "1110111";
when "1011" => segments <= "0011111";
when "1100" => segments <= "1001110";
when "1101" => segments <= "0111101";
when "1110" => segments <= "1001111";
when "1111" => segments <= "1000111";
end case;
if digit(1) = '1' then
(seg_a_out, seg_b_out, seg_c_out, seg_d_out, seg_e_out, seg_f_out, seg_g_out) <= segments;
else
seg_a_out <= 'Z';
seg_b_out <= 'Z';
seg_c_out <= 'Z';
seg_d_out <= 'Z';
seg_e_out <= 'Z';
seg_f_out <= 'Z';
seg_g_out <= 'Z';
end if;
(dig_c1_out, dig_c0_out) <= digit;
dig_0_out <= digit(1) and not digit(0);
end process;
end Hex_decode_master;
--- End code ---
Slave
--- Code: ---entity hex_decode_slave is
port(
hex_in_a: in std_logic_vector ( 3 downto 0 );
hex_in_b: in std_logic_vector ( 3 downto 0 );
dig_c0_in: in std_logic;
dig_c1_in: in std_logic;
seg_a_out: out std_logic;
seg_b_out: out std_logic;
seg_c_out: out std_logic;
seg_d_out: out std_logic;
seg_e_out: out std_logic;
seg_f_out: out std_logic;
seg_g_out: out std_logic;
dig_3_out: out std_logic;
dig_4_out: out std_logic);
attribute LOC: string;
attribute LOC of hex_in_a: signal is "5 4 3 2";
attribute LOC of hex_in_b: signal is "9 8 7 6";
attribute LOC of dig_c0_in: signal is "10";
attribute LOC of dig_c1_in: signal is "11";
-- Gnd 12
-- 13
-- 14
attribute LOC of dig_3_out: signal is "15";
attribute LOC of seg_a_out: signal is "16";
attribute LOC of seg_b_out: signal is "17";
attribute LOC of seg_c_out: signal is "18";
attribute LOC of seg_d_out: signal is "19";
attribute LOC of seg_e_out: signal is "20";
attribute LOC of seg_f_out: signal is "21";
attribute LOC of seg_g_out: signal is "22";
attribute LOC of dig_4_out: signal is "23";
-- Vcc 24
end;
architecture Hex_decode_slave of hex_decode_slave is
signal hex_in: std_logic_vector(3 downto 0);
signal segments: std_logic_vector (6 downto 0);
begin
process (dig_c0_in, dig_c1_in, hex_in_a, hex_in_b)
begin
if dig_c0_in = '0' then
hex_in <= hex_in_a;
else
hex_in <= hex_in_b;
end if;
case hex_in is
when "0000" => segments <= "1111110";
when "0001" => segments <= "0110000";
when "0010" => segments <= "1101101";
when "0011" => segments <= "1111001";
when "0100" => segments <= "0110011";
when "0101" => segments <= "1011011";
when "0110" => segments <= "1011111";
when "0111" => segments <= "1110000";
when "1000" => segments <= "1111111";
when "1001" => segments <= "1110011";
when "1010" => segments <= "1110111";
when "1011" => segments <= "0011111";
when "1100" => segments <= "1001110";
when "1101" => segments <= "0111101";
when "1110" => segments <= "1001111";
when "1111" => segments <= "1000111";
end case;
if dig_c1_in = '0' then
(seg_a_out, seg_b_out, seg_c_out, seg_d_out, seg_e_out, seg_f_out, seg_g_out) <= segments;
else
seg_a_out <= 'Z';
seg_b_out <= 'Z';
seg_c_out <= 'Z';
seg_d_out <= 'Z';
seg_e_out <= 'Z';
seg_f_out <= 'Z';
seg_g_out <= 'Z';
end if;
dig_3_out <= not dig_c0_in and not dig_c1_in;
dig_4_out <= not dig_c0_in and dig_c1_in;
end process;
end Hex_decode_slave;
--- End code ---
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