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16 bit to 4 digit 7 segment decoder
Benta:
Where are the common cathode drivers?
obiwanjacobi:
--- Quote from: Benta on January 26, 2020, 07:00:39 pm ---Where are the common cathode drivers?
--- End quote ---
Misread the NSB3881 datasheet. :palm: So I will need them.
Any recommendations for a logic level FET?
Benta:
Just use a ULN2003. It doesn't get any simpler or cheaper.
bson:
Many of the 48 pin QFP MSP430's will do this neatly, and have enough 16 bit ports to make life easy. Since it's a 16-bit processor you can stage the segment output as 16 bit data in a pattern buffer, to be output to a 16-bit port to drive the segments, and just have a DMA controller continuously scan it, possibly triggered by a timer. When the DMA gets to the end it interrupts and you restart it in the handler. Then to update the segments you write to the pattern buffer. Since each segment gets the same number of words staged in the pattern buffer this becomes simple and reliable, without potentially weird timing problems as it might if different bits in different GPIO registers are updated in sequence. Similarly on the input, a GPIO pin interrupts and you read a 16-bit I/O register. If it has changed you wake the main CPU in the interrupt handler (DMA will run in some sleep modes, and you wake it by modifying the pushed status register; TI-CCS has C macros and functions for this), save the new value (so you can detect changes), translate it to digits, convert to segment I/O words and store them to the pattern buffer, and go back to sleep.
edavid:
--- Quote from: obiwanjacobi on January 26, 2020, 07:33:27 pm ---
--- Quote from: Benta on January 26, 2020, 07:00:39 pm ---Where are the common cathode drivers?
--- End quote ---
Misread the NSB3881 datasheet. :palm: So I will need them.
--- End quote ---
What's your peak segment current? If it's 10mA, 70mA/digit is not all that far from the spec of 40mA per pin. It would probably work OK.
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