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1kW Resonant Converter - Analysis, Design, Build and Validation
Posted by sandalcandal on 01 Dec, 2020 12:44 -
Preface:
In the lead up to a larger commercial project, I'm building a "small" 1kW CLLC resonant converter as a sort of pilot to develop and test my design methods and models. This project in itself isn't intended for any practical purpose other than learning. The project is expected to be mostly an implementation following existing methods and reference designs, nothing particularly creative or secret sauce for now. There's ample existing literature out there but a lot of it is either esoteric academia or vendor white papers so hopefully I can contribute something both down-to-earth pragmatic and component vendor impartial to the community and bring people along for the ride in the process (perhaps release an open source reference at the end). Of course not being entirely altruistic, I also hope people will be able to catch any errors and provide suggestions and constructive criticism.
Index:
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Bibliography - this post[writing up]
System Specs - this post
Topology Choice - this post
Critical Component Selection - this post
First Harmonic Analysis
-Analytical Exploration - this post
-Numerical Values and Simulation - LTSpice Models
Nonlinear Time Domain Analysis
-Simplified model frequency response
Additional Component Selection - todo
System Implementation Review - todo
Subsystem Design-Testing - todo
Complete System Build - todo
Complete System Validation -todo
[more to come?]
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Questions/Footnotes:
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Inductance Required for \$C_{oss}\$ Charging - Solution by gae_31
SPICE Diodes and Convergence
Picking a DSP MCU
Light load gain
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Bibliography
Jee-Hoon Jung, Ho-Sung Kim, Ho-Sung Kim, Myung-Hyo Ryu, Ju-Won Baek "Design Methodology of Bidirectional CLLC Resonant Converter for High-Frequency Isolation of DC Distribution" IEEE Transactions on Power Electronics 28(4):1741-1755, April 2013, Section III.A (pg. 1745-1746) https://www.researchgate.net/publication/260496284_Design_Methodology_of_Bidirectional_CLLC_Resonant_Converter_for_High-Frequency_Isolation_of_DC_Distribution_Systems
H. Huang "Designing an LLC Resonant Half-Bridge Power Converter" SLUP263, Texas Instruments, 2010, pg. 15 https://www.ti.com/seclit/ml/slup263/slup263.pdf (Lm max error?)
F. Di Domeninco, J. Hancock, A. Steiner, J. Latly "600 W half bridge LLC eval board with 600 V CoolMOS™ C7 and digital control by XMC™" AN_201411_PL52_005, Infineon Technologies, 2016-04-21, pg. 25 https://www.infineon.com/dgdl/Infineon-ApplicationNote-600W-HB-LLC-Evalboard-with-C7600V-and-digital-control-by-XMC-AN-v01_00-EN.pdf?fileId=5546d46253f6505701544cc1d15c20d7 (Lm max error?)
"Bidirectional CLLLC Resonant Dual Active Bridge (DAB) Reference Design for HEV/EV Onboard Charger" TIDUEG2C, Texas Instruments, March 2020, Section 2.2.1.3 (pg. 11) https://www.ti.com/lit/ug/tidueg2c/tidueg2c.pdf
A. Scuto "Half bridge resonant LLC converters and primary side MOSFET selection" AN4720, STMicroelectronics, August 2015, https://www.st.com/resource/en/application_note/dm00207043-half-bridge-resonant-llc-converters-and-primary-side-mosfet-selection-stmicroelectronics.pdf
J. Luo, J. Wang, Z. Fang, J. Shao, J. Li "Optimal Design of a High Efficiency LLC Resonant Converter with a Narrow Frequency Range for Voltage Regulation" Energies 2018, 11, 1124. pg 5-7 https://www.mdpi.com/1996-1073/11/5/1124
Bouvier, Y.E.; Serrano, D.; Borović, U.; Moreno, G.; Vasić, M.; Oliver, J.A.; Alou, P.; Cobos, J.A.; Carmena, J. "ZVS Auxiliary Circuit for a 10 kW Unregulated LLC Full-Bridge Operating at Resonant Frequency for Aircraft Application" Energies 2019, 12, 1850. pg. 9-13 https://www.mdpi.com/1996-1073/12/10/1850 (Introduces new circuit elements to help ZVS range)
M. O'Loughlin "Improving ZVS and Efficiency in LLC Converters" SLUA923, Texas Instruments, December 2018 https://www.ti.com/lit/an/slua923/slua923.pdf (Poor estimation of Ippk)
S. Maniktala "Understanding and using LLC Converters to Great Advantage" Microsemi, 2013 https://www.microsemi.com/document-portal/doc_download/129464-understanding-and-using-llc-converters-to-great-advantage (Long winded, Conversational)
R. Nielsen "LLC and LCC resonance converters Properties Analysis Control" Runo's Power Design, August 2013 http://www.runonielsen.dk/LLC_LCC.pdf (Interesting discussion of control, also good clear engineering explanation of concepts)
System Target Specs
Input voltage: 40V-60V, 50V nominal
Output voltage: 40V-60V, 50V nominal
Power: 1kW nominal, 200W min to 1.2kW peak
Efficiency: >97% peak, >95% full range
Power density: >1kW/L
Bidirectional
Notes on Targets- Input and output voltage set around 60VDC maximum for safety (DC voltage exposure limit).
- AC intermediate and tank voltage potentially dangerous but high frequency should prevent involuntary muscle contraction, main danger of burns.
- 1:1 nominal voltage ratio for simplicity, also not far from application ratio
- 1kW power trying to stay somewhat close to final application in at least magnitude of current and thus class of components and design
- 20% minimum load similar application
- 120% load head room also desirable
- Efficiency targets just below achieved performance of other reference designs
- Would be nice to achieve and test bidirectional functionality
Topology: Dual Active Bridge CLLC
The dual active bridge CLLC topology appears to be ideal for our system requirements due to overall high performance: best efficiency, best power density and bidirectionality; this is reflected in current industry trends towards resonant CLLC conversion solutions. LLC is nearly the same topology and has less complexity but CLLC symmetry allows bidirectionality. There are known difficulties in regulating LLC converter outputs but the intended application has simple output regulation requirements (battery charging over limited range) though it would be good to have a generally applicable design/method. Galvanic isolation provided by the topology is also a bonus. The dual active bridge configuration means full bridge input drive and output synchronous rectification is used to enable maximum utilisation of components (particularly magnetics) and minimisation of losses whilst enabling bidirectionality.
Alternative PWM topologies:
Some of the other options available are PWM based conversion topologies i.e. buck-boost types (including SEPIC, Cuk, flyback), push-pull, non-resonant half bridge and non-resonant full bridge.
All these PWM options are non-resonant thus do not provide soft-switching or zero-voltage-switching (ZVS) i.e. they are hard-switching. This means the transistors used for switching are turned on under significant applied voltage. This is an issue because parasitic capacitance across the transistor causes charge to build up across the transistor with applied voltage which at turn-on is dumped through the transistor resulting to lost energy as heat and EMI. This is particularly an issue then operating at very high frequencies and voltages where this turn-on loss becomes a significant limit to system performance.
The buck-boost type topologies also rely on significant energy stored in an inductor to perform conversion which places extra demand on the magnetics used with higher DC flux and larger flux swings which tend to result in larger overall magnetics requirements and magnetics losses. By comparison, push-pull, half-bridge and full-bridge "true" transformer (not flyback mutual inductor "transformer") based topologies primarily use direct \$\frac{d\Phi}{dt}\$ flux swing coupling to perform conversion which means both flux and flux swings tend to be lower making them more suitable for higher current applications.
Buck-boost type topologies apart from flybacks are also not galvanically isolated which is potentially a safety issue in some applications.
Alternative resonant topologies are: Series resonant, Parallel Resonant, LLC and CCL.
These topologies and their variant forms use some form of resonant tank to which the output is coupled via a transformer. By performing switching across a resonant/reactive tank, switching can be coordinated such that turn-on occurs during zero voltage across the transistor. The difficulty with such topologies is that regulation of output is more complex, typically relying on frequency modulation in order to modulate impedances whilst maintaining ZVS. Between these different flavours of resonant topology, there are some different characteristics such as their response loads and frequency but among them LLC is known to be able to be tuned to have the most useful response. Sam Ben-Yaakov has a excellent video lecture on the topic here:
CLLC is simply a modification of LLC with added secondary series capacitance in order to produce symmetry.
The potential for advanced, mixed-frequency/phase/PWM control systems using modern DSP is also opening up flexibility and performance of resonant topologies.
A fairly detailed albeit not exhaustive overview of switch mode topologies with their advantages and disadvantages can be found here:
M. Kamil "Switch Mode Power Supply (SMPS) Topologies (Part I)" AN1114, Microchip Technology, 2007, http://ww1.microchip.com/downloads/en/appnotes/01114a.pdf
Note on CLLC vs CLLLC:
The topology presented and analysed by me here I think should technically be called CLLLC but terminology in the literature is inconsistent. I came across this PhD dissertation today which makes a clear distinction between the two https://vtechworks.lib.vt.edu/handle/10919/77686. However, if you search for CLLC you'll find many papers presenting and discussing circuits with a discretely modelled LC secondary tank. So far CLLC seems to be more commonly used to describe the topology I'm using here so I'm going with that term.
Critical Component Selection and Component Driven Operational Parameters
I’m taking a slightly different, (hopefully) more pragmatic approach to design compared to literature here. The optimal design is constrained by available critical components capable of handling system requirements. Thus rather than first setting operational parameters based on high level system requirements then finding components to fit calculated values, instead the highest performance components available are found first then system operating parameters adjusted to optimise their implementation.
Note on operating frequency:
Higher operating frequency means smaller capacitors and inductors can be used but increasing frequency has a limit due to increasing losses with higher operating frequency; particularly in the semiconductor and magnetic components. Lower operating frequency reduces switching losses but requires larger capacitors and inductors to reduce resonant frequency and circuit impedances. The maximum power density is achieved by selecting the components which enable highest frequency operation with acceptable losses.
Ferrite Core
Resonant frequency: ~300 kHz
Switching frequency range: 300 kHz-700 kHz
Recommended frequency range of modern power ferrites. High frequency required to achieve power density targets.
\$A_e\$ =200mm² to 600mm²
\$l_g\$ = 0.1mm to 2.0mm
\$B_{max}\$ =50mT
Specs for acceptable size and cost cores intended for HF power applications. Note \$B_{max}\$ is loss/thermally limited well below saturation for HF applications. My main contenders for core material: Epcos-TDK N49 (N87 and N97 for <500kHz), Ferroxcube 3F36, Fair-Rite 79.
Feasible inductance calculated later based on manufacturer recommended maximum flux at operating frequency, reasonable core gap, and peak magnetising current for reasonable size and cost cores.
MOSFET
\$C_{oss}\$ = 620 pF
\$t_d > t_{off}\$ = 51 ns
\[L_{m(Cossmax)}< \frac{t_d}{16 C_{oss} f_{sw(max)}} = \frac{60n}{16*620p*800k}=7.56uH \label{eq:LmCossmax} \]
Not sure about the above formula for maximum inductance required for MOSFET body diode biasing based on MOSFET output capacitance calculation. I can’t find reference with derivation nor have I been able to derive it myself can get the same value as literature.
Edit: The \$f\$ value used should actually be \$f_{r}\$ the primary series resonant frequency. \$f_{sw(max)}\$ which is larger than \$f_{r}\$ will produce a tighter bound however probably isn't actually necessary for ZVS as calculated by the above equation.
Values are from datasheet specifications of TK46A08N1. Possible alternative: CSD19503KCS.
Optimal MOSFET selected based on cost vs estimated loss balance. Beware high switching losses due to high frequency operation. An approximate power loss of a single MOSFET under hard switch-on (but not reverse recovery) for comparative purposes can be calculated:
\[P_{MOSFET} = \frac{1}{2} I_{D(RMS)}^2 R_{D(on)}+ \frac{1}{2}V_{DS} I_{D} (T_{rise}+T_{fall}) f_{sw}+ \frac{1}{2} V_{DS}^2 C_{oss} f_{sw}+ Q_{G} V_{GS} f_{sw} \label{eq:P_MOSFET}\]
Resonant Capacitor
\$C_r\$ < 400 nF
Limit based on available values for MLCC C0G capacitors. Maximum of 4 paralleled 100nF. Will need parallel capacitors to handle resonant currents. For X7R, X6S, etc. capacitors current handling is too low and less stable capacitance will cause operating point drift. Film capacitors cannot handle high frequency voltage swings; excessive heating, likely reliability issues.
First Harmonic Analysis
It is useful to analyse and understand the CLLC circuit as an approximate, linearised, first harmonic equivalent to develop a “first order” intuitive understanding of the circuit behaviour.
Above is a simplified model for a full bridge CLLC converter operating in one direction. A square wave input source feeds a series LC resonant tank in series with a transformer represented as an ideal transformer with a discrete magnetising inductance parallel to the primary winding. The transformer secondary outputs to another LC tank followed by a full bridge rectifier to a smoothing capacitor and resistive load.
The non-linear model can be simplified to the above linear network. Secondary side components are replaced with “reflected” equivalents according to the transformer ratio and the non-linear rectified DC load is replaced with an equivalent power resistive load. Equations for the linearised components are:
\[R_{ac}=\frac{8}{\pi^2} R_L\]
\[R_{ac}'=N^2 R{ac}\]
\[L_{rs}'=N^2 L_{rs}\]
\[C{rs}'=C_{rs}/N^2\]
\[V_{out}'=NV_{out}\]
Reactances are by definition:
\[X_p=j(2\pi f L_{rp} - 1/(2fCrp))\]
\[X_s'=j(2\pi f L_{rs}' - 1/(2fCrs')) = j N^2(2\pi f L_{rs}-1/(2\pi f C_{rs}))\]
\[X_m=j2\pi f L_m\]
\$j\$ is the imaginary coefficient
Gain
A “gain” M for the network can then be easily found using series-parallel simplification:
\[M = \frac{N V_{out}}{V_{in}} = \frac{V_{out}'}{V_{in}} =\frac{ X_m||(X_s'+R_{ac}')}{X_p+X_m||(X_s'+R_{ac}')} \frac{R_{ac}'}{X_s'+R_{ac}'} \label{eq:M_series_parallel}\]
\[M = \frac{X_m R_{ac}'}{X_m X_p + X_s'(X_m+X_p)+R_{ac}'(X_m+X_p)} \label{eq:M}\]
Most literature also defines a \$Q=\frac{X_p}{R_{ac}}\$ factor but I haven't found this particularly useful to cleaning up equations, better understanding general behaviour or practical application where using \$R_{ac}\$ tends to be more direct than calculating the additional \$Q\$ value.
Further Analytical Exploration
Most literature seems to skip further analytical exploration after deriving the gain function and go straight to plots with example numerical values but some general behaviours can be discerned by poking at this equation further. If you're allergic to math or otherwise have an aversion to phasor analysis then skip to the Numerical Values and Simulation section.
There are two major points of interest, resonance of the primary tank and "resonance" of the primary tank with the transformer magnetising inductance.
Resonance of the primary tank will occur at
\[f_{rp} =\frac{1}{2\pi \sqrt{L_{rp} C_{rp}}} \]
and by definition at this operating frequency \$X_p \rightarrow 0\$. If the secondary tank is matched to the primary tank \$ X_p = X_s'\$ then at this resonance we also have \$X_s' \rightarrow 0\$
Resonance of the primary tank with the transformer magnetising will occur at
\[f_{rpm} =\frac{1}{2\pi \sqrt{(L_{rp}+L_m) C_{rp}}} \]
and by definition at this operating frequency \$X_p +X_m \rightarrow 0\$.
Gain Continued
At Primary Resonance
Substituting \$X_p \rightarrow 0\$ into the equation for \$M\$ obtains the gain at resonance of primary tank
\[M_{(rp)} = \frac{R_{ac}'}{X_s'+R_{ac}'}\]
When the secondary tank is matched \$X_s' \rightarrow 0\$ this reduces to:
\[M_{(rp)} = \frac{R_{ac}'}{R_{ac}'} = 1\]
Which an also be deduced intuitively looking at the FH network. It's also noted the gain is always and completely real at this resonant frequency.
At Primary Tank + Transformer Resonance
Substituting \$X_p +X_m \rightarrow 0\$ into the equation for \$M\$ obtains the gain at resonance of primary tank with transformer magnetising inductance
\[M_{(rpm)} = \frac{R_{ac}'}{X_p}\]
A high gain can be produced at this operating point by a smaller primary impedance relative to the load resistance. Also due to the initial resonance condition \$X_m+X_p \rightarrow 0 \Rightarrow X_p=-X_m\$
\[M_{(rpm)} = \frac{R_{ac}'}{-X_m}=\frac{R_{ac}'\sqrt{(L_{rp}+L_m)C_{rp}}}{-j L_m}\]
Thus a smaller \$L_m\$ will increase gain at primary + transformer resonance at \$f_{rpm}\$. Note this \$f_{rpm}=\frac{1}{2\pi \sqrt{(L_{rp}+L_m) C_{rp}}} \$ must be lower than the primary tank resonance frequency \$f_{rp} =\frac{1}{2\pi \sqrt{L_{rp} C_{rp}}}\$ and using a much larger \$L_m>L_{rp}\$ can push this resonant frequency \$f_{rpm}\$ far down below the primary \$f_rp\$ resonant frequency. Notably \$X_s'\$ has no effect. Intuitively, a very large \$R_{ac}'\$ will result in the first harmonic network degenerating to a high Q series LC tank consisting of the primary tank and transformer magnetising inductance which at it's resonance frequency will of course resonate and produce a very large circulating current and voltage.
It is also noted that the output gain is always and completely imaginary at this operating frequency.
Load Current
At Primary + Transformer Resonance
\[I_{Rac(rpm)} = \frac{V_{out(rpm)}}{R_{ac}'} = \frac{N M_{(rpm)} V_{in}}{R_{ac}'} = \frac{N V_{in}\sqrt{(L_{rp}+L_m)C_{rp}}}{-j L_m}\]
This is not dependent on \$R_{ac}'\$ so the converter will theoretically operate at a constant current independent of load. Realistically, there will likely be a limit in output voltage due to the current in the primary + transformer tank.
Magnetising Current
The first harmonic model can also be used to derive the magnetising current \$I_m\$ which is useful for determining if the transformer field density.
\[I_m = V_{in} \frac{X_s'+R_{ac}'}{X_m X_p + X_s'(X_m+X_p)+R_{ac}'(X_m+X_p)} \label{eq:I_m}\]
At Primary Resonance
\[I_{m(rp)}=\frac{V_{in}}{X_m}\]
The \$I_m\$ will only decrease for frequencies greater than \$f_{rp}\$ since both \$X_m\$ and \$X_p\$ can only increase. Magnetising current is always and completely imaginary at primary resonance frequency.
At Primary Tank + Transformer Resonance
\[I_{m(rpm)} = V_{in} \frac{X_s'+R_{ac}'}{X_m X_p}\]
As before in the gain analysis, due to the initial resonance condition \$X_m+X_p \rightarrow 0 \Rightarrow X_p=-X_m\$
\[I_{m(rpm)} = V_{in} \frac{X_s'+R_{ac}'}{-X_m^2}\]
Supposition: This will typically be greater than \$I_{m(rp)}\$ unless \$X_s'+R_{ac}'\$ is very low since \$X_m\$ at this operating point will typically be much smaller due to lower frequency.
Also noting unlike the previously calculated values, this will have a complex (not completely imaginary or real) value.
Max Inductance
Using \$I_{m(rp)}\$ in the conventional equation for estimating maximum inductance for a core of given cross sectional area, core gap, magnetising current and maximum allowed flux density (ignoring winding window/wire size):
\[L_{m(Bmax)} < \frac{l_g B_{peak}^2 A_c}{\mu_0 I_{m(max)}^2} = \frac{2 \mu_0 V_{in}^2}{l_g B_{peak}^2 A_c \omega_r^2}\]
Reducing peak flux density will reduce losses and it can be seen that reducing peak flux density means increasing magnetising inductance. Alternatively, peak flux can be reduced by:
Increasing:- Core cross sectional area
- Frequency (will have have trade-off vs Steinmetz loss)
- Gap length
- Input voltage
LC Tank
The current and voltage in the resonant tank is also good to know to understand the stresses and likely losses in the resonant tank components.
Primary Side Current
The solution to the first harmonic network for current through the primary side inductor/capacitor is:
\[I_p = \frac{V_{in} (R_{ac}' + X_m + X_s')}{X_m X_p + X_s'(X_m+X_p)+R_{ac}'(X_m+X_p)}\]
At Primary Resonance
\[I_{p(rp)} = \frac{V_{in}(R_{ac}'+X_m+X_s')}{X_m(X_s'+R_{ac}')} = \frac{V_{in}}{X_m||(X_s'+R_{ac}')}\]
The primary current is determined by the parallel impedance of the magnetising inductance and secondary side impedance as one would expect. Maintaining a higher magnetising inductance for the
transformer will ensure the tank current does not become excessive under no load (as with a normal transformer).
At Primary Tank + Transformer Resonance
\[I_{p(rpm)} = \frac{V_{in}(R_{ac}'+X_m+X_s')}{X_m X_p} = \frac{V_{in}(R_{ac}'+X_m+X_s')}{-X_m^2} \]
As with primary current at primary resonance, the current is determined by magnetising inductance impedance and total secondary side impedance Xs'+Rac' but the proportionality to secondary side impedance is flipped so larger impedance results in larger current rather than smaller.
Also if \$X_s' = X_p\$ then \$ X_m+X_s' \rightarrow 0 \$
\[I_{p(rpm)} = \frac{V_{in}R_{ac}'}{-X_m^2} \]
Note this current will be completely real i.e. there will be no reactive current circulating in the tank. This also implies all input power must be dissipated via the load resistor.
Voltage Across Capacitor
Capacitors are typically components with limited voltage handling capability and in the resonant tank, the capacitor could be exposed to voltages much higher than the input.
\[V_{Crp} = I_p X_{Crp} = \frac{V_{in} X_{Crp}(R_{ac}' + X_m + X_s')}{X_m X_p + X_s'(X_m+X_p)+R_{ac}'(X_m+X_p)}\]
We can also write this as a gain:
\[m_{Crp} = \frac{V_{Crp}}{V_{in}} = \frac{X_{Crp}(R_{ac}' + X_m + X_s')}{X_m X_p + X_s'(X_m+X_p)+R_{ac}'(X_m+X_p)} \]
Gain at the two resonant points is similar to the primary current but now with the capacitor impedance factor.
At Primary Resonance
\[m_{Crp(rp)} = \frac{X_{Crp}(R_{ac}'+X_m+X_s')}{X_m(X_s'+R_{ac}')} = \frac{X_{Crp}}{X_m||(X_s'+R_{ac}')}\]
If smaller \$C_{rp}\$ is used or magnetising inductance is low or load impedance is low then resonant capacitor voltage increases.
At Primary Tank + Transformer Resonance
\[m_{Crp(rp)} = \frac{X_{Crp}(R_{ac}'+X_m+X_s')}{-X_m^2} \]
If smaller \$C_{rp}\$ is used or magnetising inductance is low then resonant capacitor voltage increases and lower secondary side impedance \$R_{ac}'+X_s'\$ increases resonant capacitor voltage.
If \$X_s' = X_p\$ then \$ X_m+X_s' \rightarrow 0 \$
\[m_{Crp(rp)} = \frac{X_{Crp} R_{ac}'}{-X_m^2} \]
Unlike primary current at \$f_{rpm}\$, this will be completely imaginary.
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Numerical Values and Simulation
Putting some previously defined values into the equations to get some numbers.
\$R_{DCmin}=V_{INmin}^2/P{max}=402/1200=1.33 Ω\$
\$R_{DCnom}=V_{INnom}^2/P{nom}=502/1000=2.5 Ω\$
\$R_{DCmax}=V_{INmax}^2/P{min}=602/200=18 Ω \$
\$R_{acmin}=(8/\pi^2)R{DCmin}=(8/\pi^2)1.33=1.08 Ω\$
\$R_{acnom}=(8/\pi^2)R{DCnom}=(8/\pi^2)2.5=2.02 Ω\$
\$R_{acmax}=(8/\pi^2)R{DCmax}=(8/\pi^2)18=14.6 Ω\$
Getting the minimum required resonant inductance from the maximum allowed resonant capacitance:
\[f_r=\frac{1}{2\pi \sqrt{LC}}\]
\[ L_{r(Crmax)}=\frac{1}{(2\pi^2 f_r)^2 C_{r(max)}} = \frac{1}{(2\pi300k)^2 400n} = 0.7uF \]
Resonant inductance will need to be higher than this minimum to ensure resonant frequency is at or below target. Quite close to 10% of \$L_{m(Cossmax)}\$ which means it may be possible to use leakage inductance of the transformer for the resonant inductance.
Let \$L_m = 7 uF\$ and let the primary and secondary side resonant tanks be equal.
Primary Tank + Transformer Resonance will occur at
\[f_{rpm} = \frac{1}{2\pi \sqrt{(L_{rp}+L_m) C_{rp}}} = \frac{1}{2\pi \sqrt{(0.7u+7u) 400n}} = 90.7 kHz \]
Also made the first harmonic approximation circuit in LTspice for AC analysis to cross check the results from the analytically derived equations and get a more complete picture of the behaviour of the first harmonic approximation. Download LTSpice Models here.
Gain
At Primary Resonance
Since the primary and secondary tanks are matched
\[M_{(rp)} = 1\]
At Primary Tank + Transformer Resonance with \$R_{acmax}=14.6 Ω\$ there will be a gain.
\[|M_{(rpm)}| = \frac{R_{ac}'\sqrt{(L_{rp}+L_m)C_{rp}}}{L_m} = \frac{14.6\sqrt{(0.7u+7u)400n}}{7u} = 3.66\]
The simulation gives the gain at primary resonance of 59.94/60=0.98 and gain at primary + transformer of 221/60=3.68 which is 0.02 off the analytically calculated values. Fairly close but not perfect alignment between simulated and analytically derived results, possibly just rounding error?
Additionally as expected from the analytical exploration, the gain at resonance is stable/independent of the load. It is also completely real (\$-180^\circ\$ phase). At primary + transformer resonance the phase of the output is completely imaginary (\$-90^\circ\$ phase); also as predicted in the analytical exploration.
Magnetising Current
At Primary Resonance and maximum input voltage
\[I_{m(rp)} = \frac{V_{in}}{X_m}=\frac{60}{- j 2\pi*300k*7u} = -j 4.55 A\]
Magnetising current in simulation is slightly lower than than the analytically derived value possibly due to rounding errors in calculations. Following analytical exploration expectations, the current is stable/independent of load and completely imaginary (\$-90^\circ\$ phase).
At Primary Tank + Transformer Resonance with \$R_{acmax}=14.6 Ω\$ and maximum input voltage
\[I_{m(rpm)} = V_{in} \frac{X_s'+R_{ac}'}{-X_m^2} = 55.1 - j 15.0 \Rightarrow |I_{m(rpm)}|= 57.1 A\]
The simulated magnetising current of 57.0 A is again close to the value derived in analytical derivation but it can be seen that the local peak is actually at a lower frequency and for high loads (low load resistance) there is significantly higher current peaks at even lower frequencies. These appear to correspond to the smaller lower frequency peaks visible in the output voltage response. I'm not sure what this frequency or combined resonance relates to since its is so low and seems to go down with lower load resistance which is not something I'd expect interactions with the matched secondary tank to do. However, it's likely not relevant to the actual applied circuit since it's well below the operating frequency range so I might leave it for the time being though other people are free to explore it.
There also seems to be a stable current point around 75.2 kHz, again not sure what this relates to.
Tank Current
At Primary Resonance, maximum input voltage and \$R_{acmin}=1.08 Ω\$
\[I_{p(rp)} = 55.6-j4.53\Rightarrow |I_{p(rp)}| = 55.7 A\]
Note at this operating point, output power will be \$60^2/1.08=3333\$ W
At Primary Tank + Transformer Resonance with \$R_{acmax}=14.6 Ω\$ and maximum input voltage
\[I_{p(rpm)} = 55.1 A\]
Again, simulation and analytically derived values are quite close. The actual peak near primary + transformer resonance with maximum load resistance is however lower frequency and higher as it was with magnetising current. Phase is confirmed to be stable and completely real however.
Tank Capacitor Voltage
At Primary Resonance, maximum input voltage and \$R_{acmin}=1.08 Ω\$
\[m_{Crp(rp)} = -0.1 - j 1.22 \Rightarrow |m_{Crp(rp)}| = 1.23\]
Note at this operating point, output power will be \$60^2/1.08=3333\$ W
At Primary Tank + Transformer Resonance with \$R_{acmax}=14.6 Ω\$ and maximum input voltage
\[m_{Crp(rpm)} = - j 4.02\]
73.63/60=1.23 and 246.29/60=4.10 so again simulation and analytically derived values are quite close but even for the primary resonance this time, the actual peak is lower frequency perhaps due to influence of the magnetising inductance dragging response lower? Should perhaps do analysis of differential wrt to frequency in order to find relationship of component values to peaks. I don't recall seeing much discussion of such minutia in literature however.
Nonlinear Time Domain Simulation
[Writing up, preview results below using different value components]
Square Wave Input - Rectified Output
MOSFET Input - Rectified Output
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Question 1
Inductance Required for Combined Coss Charging
ZVS in an LLC or CLLC circuit relies on inductive current being present in the primary tank and/or the transformer magnetising inductance such that when the input driving MOSFET pair is turned-off the inductive current will cause a reversal of voltage across the primary tank + transformer forcing reverse biasing of MOSFET body diodes (or "true" zero voltage if timing is perfect) in the alternate MOSFET pair before they are turned-on. This turn-off, reversal, turn-on cannot happen instantaneously due to a variety of factors including MOSFET output rise/fall time and importantly here, the need to charge/discharge MOSFET output capacitances, thus there needs to be a "dead time" period between initiating turn-off of one MOSFET pair and turn-on of the alternate MOSFET pair to allow time for the voltage reversal to occur.
\[L_{m(Cossmax)}< \frac{t_d}{16 C_{oss} f_{sw(max)}}\]
Not sure about the formula for \$L_{m(Cossmax)}\$ the maximum inductance allowed such that MOSFET output capacitance \$C_{oss}\$ can be charged within the dead time \${t_d}\$ so that ZVS is achieved. I can’t find a reference with the full derivation and there seems to be conflicting information in the literature. My closest derivation (which is the one shown above) is a factor of 2 higher than values shown in literature. The equation shown in literature is the same as above but is being provided for a half bridge circuit which is half the total effective capacitance to be charged i.e. for HB: Ceq=2Coss+Cstray but for FB: Ceq=4Coss+Cstray. The above is derived using peak magnetising current available to charge combined Coss at start of dead time.
For the “complete” non-linear time-domain picture of an LLC with full bridge input and full bridge rectified output, operating near primary tank resonance, the magnetising “inductor” of the transformer will see a square wave with amplitude \$n V_{out}=V_{in}\$ with a period \$ T_{sw} = \frac{1}{f_{sw}}\$. The magnetising inductor current \$I_m\$ will thus rise to a peak value just before switching and dead-time:
\[I_{m(pk)}=\frac{N V_{out}}{L_m}\frac{T_{sw}}{4} \text{(Current in inductor, constant voltage)}\]
Supposition: This will be the minimum current available available during dead time unless operating at extreme frequencies (relative resonance) [footnote 1] This current must be able to discharge the output capacitances of the MOSFETs plus any additional stray capacitances within the dead-time in order to flip the voltage and achieve zero-voltage turn-on for the alternate MOSFET pair i.e. the charge delivered by the magnetising inductor current \$q_{m(d)}\$ during dead-time \$t_d\$ must be equal to or greater than the total charge of the MOSFET outputs and stray capacitances \$ q_{eq} \$.
\begin{align*}
q_{m(d)} &\geq q_{eq}\\
I_{m(pk)} t_{d} &\geq C_{eq} V_{in}
\end{align*}
Let \$C_{stray} = 0\$
\begin{align*}
\frac{N V_{out}}{L_m}\frac{T_{sw}}{4} t_{d} &\geq 4 C_{oss} V_{in}\\
L_{m} &\leq \frac{t_d T_{sw}}{16 C_{oss}}\\
L_{m(Cossmax)} &\leq \frac{t_d}{16 C_{oss} f_{sw(max)}}\\
\end{align*}
Again, for circuits where this is shown in literature, it is generally shown with a half bridge so \$C_{eq} = 2C_{oss}\$ instead and this derivation would yield.
\[L_{m(Cossmax)} \leq \frac{t_d}{8 C_{oss} f_{sw(max)}}\]
Thus there is a factor of 2 discrepancy.
There is another possible derivation which seems to be implied in the literature of a similar value where the condition is instead: the inductive energy of the transformer magnetising inductance \$E_L\$ must be greater than the capacitive energy of the MOSFET output capacitance \$E_C\$.
\[E_L = \frac{1}{2} L_m I_{m(pk)}^2 = \frac{V_{in}^2}{L_m}\frac{T_{sw}}{32}\]
\[E_C = \frac{1}{2} C_{eq} V_{in}^2 = 2 C_{oss} V_{in}^2\]
\begin{align*}
E_L &\geq E_C \\
\frac{V_{in}^2}{L_m}\frac{T_{sw}}{32} &\geq 2 C_{oss} V_{in}^2 \\
L_{m} &\leq \frac{T_{sw}^2}{64 C_{oss}}
\end{align*}
Note there is no \$t_d\$ is this upper limit for \$L_m\$. For the previously derived equation for \$L_{m(Cossmax)}\$ to be equivalent, \$t_d = \frac{T_{sw}}{4}\$ and if the dead time is any shorter than one quarter switching period \$t_d<\frac{T_{sw}}{4}\$ (which is quite likely to be the case) then the previously defined \$L_{m(Cossmax)}\$ will be a tighter bound. So this upper limit of transformer magnetising inductance based on energy is not relevant.
Any idea on where I've made a mistake or the equation in literature comes from? Given there are at least some papers supporting my personally derived value I think I'm going to keep going with what I have for the time being and assume the literature contrary is wrong.
Update: Solution from gae_31 here The mistake I made was forgetting that for the half-bridge, \$\frac{V_{out}}{V_{in}}= \frac{1}{2N}\$ not \$\frac{V_{out}}{V_{in}}= \frac{1}{N}\$ as in the full bridge which results in a compensation for difference in inverter total capacitance as pointed out by gae_31
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Note: Not all design white papers and discussion of LLC or CLLC design seem to even consider this ZVS requirement condition.
Footnote 1: Rough reasoning: At primary resonance, during dead-time this peak magnetising inductance current will be equal to the primary current since primary tank is at resonance thus will have zero voltage and be unable to contribute to the voltage inversion AND the primary current during dead time will increase for higher or lower frequencies up to extremes as phase of the tank current shifts out of sync with the input drive. Also note you can't just look at amplitudes in the first harmonic phasor analysis because we need to find current around the input drive switching point. Some evidence should be visible in time-domain simulations I'll post later.
References
Jee-Hoon Jung, Ho-Sung Kim, Ho-Sung Kim, Myung-Hyo Ryu, Ju-Won Baek "Design Methodology of Bidirectional CLLC Resonant Converter for High-Frequency Isolation of DC Distribution" IEEE Transactions on Power Electronics 28(4):1741-1755, April 2013, Section III.A (pg. 1745-1746) https://www.researchgate.net/publication/260496284_Design_Methodology_of_Bidirectional_CLLC_Resonant_Converter_for_High-Frequency_Isolation_of_DC_Distribution_Systems (Seems to agree with my result)
H. Huang "Designing an LLC Resonant Half-Bridge Power Converter" SLUP263, Texas Instruments, 2010, pg. 15 https://www.ti.com/seclit/ml/slup263/slup263.pdf (analysing HB but has factor 16 instead of 8 which it should according to my analysis, mentions energy but no derivation substantiated)
F. Di Domeninco, J. Hancock, A. Steiner, J. Latly "600 W half bridge LLC eval board with 600 V CoolMOS™ C7 and digital control by XMC™" AN_201411_PL52_005, Infineon Technologies, 2016-04-21, pg. 25 https://www.infineon.com/dgdl/Infineon-ApplicationNote-600W-HB-LLC-Evalboard-with-C7600V-and-digital-control-by-XMC-AN-v01_00-EN.pdf?fileId=5546d46253f6505701544cc1d15c20d7 (analysing HB but has factor 16 instead of 8 which it should according to my analysis, no derivation substantiated)
"Bidirectional CLLLC Resonant Dual Active Bridge (DAB) Reference Design for HEV/EV Onboard Charger" TIDUEG2C, Texas Instruments, March 2020, Section 2.2.1.3 (pg. 11) https://www.ti.com/lit/ug/tidueg2c/tidueg2c.pdf (Seems to agree with my result but gives no derivation or citation)
Other \$C_{oss}\$ based ZVS condition equations:
A. Scuto "Half bridge resonant LLC converters and primary side MOSFET selection" AN4720, STMicroelectronics, August 2015, https://www.st.com/resource/en/application_note/dm00207043-half-bridge-resonant-llc-converters-and-primary-side-mosfet-selection-stmicroelectronics.pdf (Incomplete derivation, no Lm bound)
J. Luo, J. Wang, Z. Fang, J. Shao, J. Li "Optimal Design of a High Efficiency LLC Resonant Converter with a Narrow Frequency Range for Voltage Regulation" Energies 2018, 11, 1124. pg 5-7 https://www.mdpi.com/1996-1073/11/5/1124 (I think equation 21 becomes the same as my result if equation 19 is substituted in)
Bouvier, Y.E.; Serrano, D.; Borović, U.; Moreno, G.; Vasić, M.; Oliver, J.A.; Alou, P.; Cobos, J.A.; Carmena, J. "ZVS Auxiliary Circuit for a 10 kW Unregulated LLC Full-Bridge Operating at Resonant Frequency for Aircraft Application" Energies 2019, 12, 1850. pg. 9-13 https://www.mdpi.com/1996-1073/12/10/1850 (Incomplete derivation for q_oss ZVS, introduces new circuit elements to help ZVS range)
M. O'Loughlin "Improving ZVS and Efficiency in LLC Converters" SLUA923, Texas Instruments, December 2018 https://www.ti.com/lit/an/slua923/slua923.pdf (Poor estimation of Ippk)
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\[L_{m(Cossmax)}< \frac{t_d}{16 C_{oss} f_{sw(max)}}\]
Not sure about the formula for \$L_{m(Cossmax)}\$ the maximum inductance allowed such that MOSFET output capacitance \$C_{oss}\$ can be charged within the dead time \${t_d}\$ so that ZVS is achieved. I can’t find a reference with the full derivation and there seems to be conflicting information in the literature. My closest derivation (which is the one shown above) is a factor of 2 higher than values shown in literature.
FWIW, this expression can be imagined as the geometric mean of t_d, as if it were a frequency ~1 / (2.5 t_d), with f_sw(max). Then at the resonant frequency, you have L = 1 / ((2 pi F)^2 C), of course the geometric mean Fm = sqrt(F1 F2) expands through the squared frequency giving the above expression, the coefficient being rounded to a whole number.
As for where the 2.5 comes from, I don't know.
Anyway, a direct analytical solution isn't possible because capacitance varies massively with voltage. (At least, unless a function is provided for that, and if it's soluble...) Next best thing is numerically approximating an equivalent capacitance, at a given supply voltage (which is fortunately quite reasonable here).
Note that, when inverter/rectifier current is real, there's very little reactive current at the switching edge and ZVS may not occur, so there may be good reason to avoid resonance exactly, keeping the phase inductive instead. This puts a value somewhere between Lm and Ls in play, which helps as far as keeping t_d small. But also, in general calculating or adjusting it dynamically, isn't very reasonable (it could be done with a DSP or FPGA), so we should even want to guard-band it from both sides. (I... don't think it should rebound off the rails, there shouldn't be any higher resonant modes* to do that? So a worst-case should suffice, and we don't have to worry about taking too long to turn on the transistor.)
*Though at high voltages, the self-capacitance of the transformer may cause problems with that?
But also, you haven't discussed controls yet, so that's its own matter and I'm getting ahead of things.
I don't have too much experience with these, but the design of this seemed to be straightforward:
Schematic: https://www.seventransistorlabs.com/Images/ResonantSupplySch.png
Rectifier not shown here; it's a full wave doubler for 20-30V output, and a few 10uF ceramics for filtering. Feedback is shown, and just a dumb zener for simplicity (select 18-27V zener to cover that range, of course).
I wanted to make a converter with planar magnetics, at a frequency high enough where a coreless Ls was reasonable, and keeping the transformer small. (I was also worried that, given the limited turns of the planar design, core losses would demand high Fsw; but the Ls losses actually dominate, so it turns out I can run at much lower frequency after all.) So it runs at 2-3MHz.
But even worse, it turns out the combination of too-large silicon MOS gates, and linear instead of switching reg supply, kills all the efficiency -- for a ~10W output, the driver alone dissipates a watt or two.
So the overall efficiency is pretty shite, like 67%. Ah well...
I haven't played with it in a while, I suppose the next thing to try might be dropping Fsw, which requires an external Ls (obviously I can't modify the in-board one; as you can see above, I also tested one of magnet wire), somewhat more Lm (the core is ungapped so this is easily adjustable, L2), and more C23 (which isn't as easy, being a largeish C0G, but I can stack two maybe three for testing).
Would also be a good place to try GaN, which if there were some available in the same package and footprint, I could probably just drop in, actually. The 6V drive would be a little high but that could be reduced, and D1 shorted, to keep everything happy.
Also, I didn't see a lot of resonant controllers that looked reasonable for making a testing circuit like this, so I made a discrete one instead. It's a variable frequency control, with an upper limit transitioning to hysteretic mode, following the behavior of L6599 which I had seen earlier. It seems to sit in hysteretic mode for the most part, which I'm not sure if that's because it's simply powerful enough that it doesn't need to drop towards resonance, or if I've mismatched the tuning and VCO range.
And yes, the driver has deadtime built in, handy, though also not adjustable. With small transistors here, I'm not too worried about Coss energy.
Tim -
Continuing from post on other thread
Specifically, a poled dielectric: an electret. Some of these (the earlier series?) are poled at the factory, and must not be heated to the Curie temperature during soldering, meaning they must be hand soldered, and carefully at that. Others, I don't know how it is they work, but they make the poling voltage/temperature such that they pick it up on first use, and these can be reflow soldered normally.
What was the max temperature limits for those? Ceralink datasheet shows it to be rated for a pretty standard reflow soldering, 260C peak and 150C operating temperature max. They're based on a PLZT ceramic and claim to function based on antiferroelectric material property where "Permanent dipoles form antiparallel zones" https://www.tdk-electronics.tdk.com/download/1195592/1753c455d19f9c7e635942c9cfba0318/ceralink-presentation.pdfFor example, look up Google Little Box. IIRC, the winning team used these, combined with a GaN inverter, to do what amounts to shunt PFC on the DC input -- one of the curious specs of the challenge was a particularly low input ripple, necessitating energy storage for a full inverter output line cycle. Their solution used less space, in total, than electrolytic capacitors you'd need to do just this passively!
I remember seeing some funky input filtering in a Google Little Box entries where there was a switched LC used to do "PFC but on DC input" as you say. A potential option but I'm hoping to get away with just a high degree of multiphase (looking like 12 phases) for my final application which seems to be optimal anyway when considering available components/materials and their costs and will probably be enough of a control system challenge.For resonant, type 2 dielectric are no good. You need C0G, but availability sucks in low voltages and high values. (Incidentally, they have higher energy density than most anything else, if you're using a few hundred volts -- it might even be worthwhile putting taps on those inductors so you can make use of this!) Next best is film, which, SMT films suck ($$) so consider PP in THT. You can get some quite beefy pulse and snubber type caps (Illinois PPB comes to mind, or a few series by EPCOS/TDK but I don't remember what numbers). Though again maybe not in low voltages.
C0G was my choice for resonant capacitor if you see my main project post. For final application voltage and acceptable capacitance for my desired operating frequency they seem to have the best performance and costs are at acceptable levels. Availability hasn't looked too sketchy so far *touch wood*. I'm using C0G in the lower voltage pilot to try expose myself to any potential issues and get some experience.
With film, at the final application voltage (>300V) dielectric losses seem too excessive. The datasheets I've seen have ripple voltage derating at HF which make them practically useless. However, performance could be acceptable for input/output smoothing and $/uF is much lower than MLCC so some MKP are my main contenders for input/output smoothing.The last possibility is aluminum polymer, which serves a very similar role to film caps, but at low voltages and respectively higher values -- they have similar energy density. The tan delta (~= 1/Q) may not be enough, though (which is also to say, respect the ripple current ratings). And they don't like much reversal, so you'd have to use anti-series pairs with DC bias.
Aluminium polymer is an interesting option I didn't consider. High values in the range offered by electrolytic caps don't seem necessary for the resonant tank and I'd have reliability questions trying to use an anti-parallel pair. Furthermore, with my final application (>300V) the available voltage ratings don't seem suitable.
If the final application circuit was 50Vnom some of the choices are probably sub-optimal but the main purpose of that pilot project is to get experience with a smaller subset of challenges and hopefully be able to work quicker with less safety barriers before trying to tackle the full problem. -
Thanks Tim
Note that, when inverter/rectifier current is real, there's very little reactive current at the switching edge and ZVS may not occur, so there may be good reason to avoid resonance exactly, keeping the phase inductive instead. This puts a value somewhere between Lm and Ls in play, which helps as far as keeping t_d small.
The value I derived for \$L_{m(Cossmax)}\$ is based on the resonant operating point i.e. no reactive current in the primary tank and current "driven" by transformer magnetising inductance. Satisfying this condition means ZVS can be sustained through primary tank resonance. When I post some time-domain simulation waveforms it should be a bit more obvious how it works. I don't have much of a hard analytical proof this will be a minima though.But also, in general calculating or adjusting it dynamically, isn't very reasonable (it could be done with a DSP or FPGA), so we should even want to guard-band it from both sides. (I... don't think it should rebound off the rails, there shouldn't be any higher resonant modes* to do that? So a worst-case should suffice, and we don't have to worry about taking too long to turn on the transistor.)
I've seen some papers where they do variable dead time to improve performance so I might give it a shot in the far future but for the time being I'll be focusing on getting a minimally functional circuit and building up from there.Also, I didn't see a lot of resonant controllers that looked reasonable for making a testing circuit like this, so I made a discrete one instead. It's a variable frequency control, with an upper limit transitioning to hysteretic mode, following the behavior of L6599 which I had seen earlier. It seems to sit in hysteretic mode for the most part, which I'm not sure if that's because it's simply powerful enough that it doesn't need to drop towards resonance, or if I've mismatched the tuning and VCO range.
For control I'm looking at using DSP with a real time MCU which seems to be the current industry flavour and should allow the maximum configurability and controllability for rapid prototyping. I have colleagues that do have some experience doing formal verified programming so hopefully they can help get a reasonable robust code. -
Would also be a good place to try GaN, which if there were some available in the same package and footprint, I could probably just drop in, actually. The 6V drive would be a little high but that could be reduced, and D1 shorted, to keep everything happy.
6Vgs is actually ideal for the good GaN FETs I've seen e.g. https://gansystems.com/gan-transistors/gs61008t/ Qg = 8 nC, Rds(on) = 7 mohm, (@Vgs=6) $US6.73 1ku. Bloody expensive but that's top of the line performance and might be necessary since you're working up at MHz.
One of the things I'm not sure about when using GaN in resonant converters is due to the lack of body diodes the tank voltage isn't clamped to the rails so during dead time so you'd seem to need early turn-on to ensure you don't break the FETs with inductive voltage rise. I did see one reference design using GaN in an LLC which seemed to work https://www.infineon.com/cms/en/product/evaluation-boards/eval_3k6w_llc_gan/ but its a bit light on implementation details and I didn't see them doing anything special for control so I'm not sure how they avoided that potential issue. The errata on that page indicates problems with failures in soft switching applications including LLC so I wonder if this is the cause but then the waveforms in the user guide don't seem to have any spikes at turn-off. GaN seems most common in hard-switching topologies where the lack of body diode and very low parasitic capacitances help but are otherwise limited by maximum voltage.Also, I didn't see a lot of resonant controllers that looked reasonable for making a testing circuit like this, so I made a discrete one instead. It's a variable frequency control, with an upper limit transitioning to hysteretic mode, following the behavior of L6599 which I had seen earlier. It seems to sit in hysteretic mode for the most part, which I'm not sure if that's because it's simply powerful enough that it doesn't need to drop towards resonance, or if I've mismatched the tuning and VCO range.
That discrete control circuitry looks impressive but seems to be taking up a lot more space than the actual power components, not much other options if you're going for an analog control circuit though I guess. -
6Vgs is actually ideal for the good GaN FETs I've seen e.g. https://gansystems.com/gan-transistors/gs61008t/ Qg = 8 nC, Rds(on) = 7 mohm, (@Vgs=6) $US6.73 1ku. Bloody expensive but that's top of the line performance and might be necessary since you're working up at MHz.
That thing's stonking massive... 200W or so, as well? Damn, hard to even switch that much power in the mere nanoseconds available -- even the say 2nH of loop inductance you'll get (with, say, a pair of them on opposite sides of a multilayer board, right beside bypass caps) is ponderous at those rates.
I was thinking just some of those grain-of-sand eGaN parts, those would have comparable ratings to what I did above.
Which, for something of the size you're working with, some of the bigger eGaN parts would be fine as well, if you can control the losses well enough that the puny die is enough heat dissipation area...QuoteOne of the things I'm not sure about when using GaN in resonant converters is due to the lack of body diodes the tank voltage isn't clamped to the rails so during dead time so you'd seem to need early turn-on to ensure you don't break the FETs with inductive voltage rise.
Not a problem -- notice the reverse characteristics, the Vgs=6 curve of course just extends the forward drain curve backwards (through zero), but the others are basically the same, shifted by Vgs(th) (and a bit more sloped, not actually shifted, because y_fs is a term in it as well).
In other words, these substrate-less FETs don't have any body diode, they just work as any other FET does, in inverted mode. If Vgs(off) = 0V, you can think of it as a relatively high drop schottky -- instantaneous, no recovery, majority-carrier operation. For the few ns of deadtime where this is active, I wouldn't worry about it; it will affect efficiency, and maybe the extra "tit" on the waveform contributes to EMI, but it doesn't go any further than that, not a reliability problem or anything.
Definitely, none are rated for avalanche though -- they're all very tiny dies besides, even that one shows a rapidly shrinking SOA (notice the curves, 0.7us, 50us and DC!), not like you'd get much energy even if they were -- so a judicious safety margin, and big beefy TVS, should be a wise idea.QuoteGaN seems most common in hard-switching topologies where the lack of body diode and very low parasitic capacitances help but are otherwise limited by maximum voltage.
Yup, and of course they allow resonant to ever-higher frequencies, like pushing 10 or even 10s of MHz. As miraculous as they are, they suffer the same tradeoff of any power switching device, that capacitances are relatively high, making loop inductance that much more critical; and at some point you just can't run any more (MHz or W) without either exceeding Vds(max), or burning up far too much switching loss (in the devices, or in snubbers; and we're talking loop inductances that can't physically be snubbed with standard components, so good luck with that!).QuoteThat discrete control circuitry looks impressive but seems to be taking up a lot more space than the actual power components, not much other options if you're going for an analog control circuit though I guess.
Yeah, and it can be shrunk a bit with smaller components, resistor packs and such, or offloaded to a riser board; or better still, replaced with an appropriate IC. But this was a good approach for testing, and as you can see it got a little messy from trying different parts, so the size was worthwhile.
But I digress; looking forward to your next section.
I'm curious to see... what's next, analysis of synchronous rectification? This is slightly different from the LLC I tried, as the C is placed symmetrically; that should help simplify things with synchronous drive, and I don't know offhand what effect not just frequency but phase also plays this way.
I suppose in analogy to AC power systems, one could have a load which is actually a source (indeed will, as you say this is to be bidirectional), or which has a reactive characteristic thanks to its phase. Perhaps that reactive power can be used to enforce ZVS over wider operating ranges?
Also, regarding your first question, but still not really answering it I'm afraid -- note that Eoss varies wildly with bias voltage too. So I'm not sure that an energy argument is so useful in general, here. Specifically, the commutation energy depends on the instantaneous voltage in Crp.
Probably it would be sufficient to take the worst possible value of both cases (which really just means, between VBUS/2, and 0 or VBUS which are symmetrical).
And even if it doesn't fully commutate (to <= 0V or >= VBUS), if it gets close by the time the transistor switches on, it's still saving some effort -- there's a lot less Eoss very close to the rail (and with respect to it) than over the whole range.
Also to say, the most important thing is to avoid hard switching from near the opposite rail, because charging a large capacitance to the far rail takes a huge slug of current, which dissipates a lot more switching loss, and that current excites the switching loop inductance (so may cause ringing).
Tim -
Nice Topic
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That thing's stonking massive... 200W or so, as well? Damn, hard to even switch that much power in the mere nanoseconds available -- even the say 2nH of loop inductance you'll get (with, say, a pair of them on opposite sides of a multilayer board, right beside bypass caps) is ponderous at those rates.
I saw TI has an integrated (co-packaged?) driver + GaN FET they're advertising recently that does 150V/ns switching
To be clear, when discussing "eGaN" we're talking about discrete enhancement mode FETs using an GaN which generally seem to use a eHEMT construction right? I guess all the power GaN FETs that are in fashion right now are all eHEMT?Not a problem -- notice the reverse characteristics, the Vgs=6 curve of course just extends the forward drain curve backwards (through zero), but the others are basically the same, shifted by Vgs(th) (and a bit more sloped, not actually shifted, because y_fs is a term in it as well).
Ah yes, I see it now. For these no body diode FETs there's a whole additional set of curves in the datasheets for reverse conduction and with Vgs=0 you still get a reverse conduction albeit at a fairly high Vsd. I wonder if this high Vsd conduction is the cause or at least contributes to apparent reliability problems in soft switching topologies. I need to correct my intuition of FETs.Definitely, none are rated for avalanche though...
Good to point out. As per the the GaN Systems datasheet: "All GaN E-HEMTs do not avalanche and thus do not have an avalanche breakdown rating."Yup, and of course they allow resonant to ever-higher frequencies, like pushing 10 or even 10s of MHz. As miraculous as they are, they suffer the same tradeoff of any power switching device, that capacitances are relatively high, making loop inductance that much more critical; and at some point you just can't run any more (MHz or W) without either exceeding Vds(max), or burning up far too much switching loss (in the devices, or in snubbers; and we're talking loop inductances that can't physically be snubbed with standard components, so good luck with that!).
I might be looking at the problem wrong but for the power/current levels I'm looking at, ferrite core losses seem to be a limiting factor well before pushing into multi MHz territory.I'm curious to see... what's next, analysis of synchronous rectification? This is slightly different from the LLC I tried, as the C is placed symmetrically; that should help simplify things with synchronous drive, and I don't know offhand what effect not just frequency but phase also plays this way.
Two (or more) steps ahead of me there with the synchronous rectification (SR). Still need to document (and in doing so double check) how input driving works and the ways in which ZVS seems to come apart as well as how well the first harmonic approximations carry to a more complete time-domain model. Haven't even really thought about how the secondary side tank is going to mess with SR but given there are multiple existing reference designs this hopefully won't be too much of a challenge...Also, regarding your first question, but still not really answering it I'm afraid -- note that Eoss varies wildly with bias voltage too...
The goal is to determine bounds for component values which ensure ZVS can occur over the operating range. No need for an expression that is true everywhere, just something which is a tight enough bound so correct operation can be ensured over the operating range. We need to figure out the worst case during operation and quantify a bound based on that which hopefully that \$L_{m(Cossmax)}\$ does. Below primary tank resonance, phase offset will start to throw things under the bus with primary current reversing itself before switching which just makes ZVS impossible. I'd better post those detailed time-domain sims... -
Bonjour SandalCandle and T3sl4co1l!
I was a power supply designer in 1970s..1990s. Only resonant @ 500 kHz were for the Metcla solder irons 30W and a 70W arc lamp ballast. So I am a bit outdated!
Very fine analysis, a bit hard to read as separate posts in a forum. please consider an web blog/website post, article or paper when its finished.
A few questions please:
1/ Freq/MOSFET: Did you consider the newer technologies such as GasFET and SiC FET?
They use much higher switch freq and offer better efficiency, at the tradeoff of higher cost.
2/ Ferrite choice: The materials mentioned seem to be very old (Siemens N numbers) or from firms that ceased operations.
Modern TDK numbers are starting with PC eg PC 200. TDK ferrite cores are readily available in USA from MH&W.
https://product.tdk.com/info/en/products/ferrite/ferrite/ferrite-core/technote/pov_pc200.html
3/ Papers and refs: Did you search the IEEE transactions on Power Electronics, or APEC and other power electronics conferences? Especially an old friend and colleague, Dr Richard REDL, has been active for decades in papers, research and seminars on resonant converters.
4/ Can you discuss further your choice of CLLC topology vs other choices and the tradeoffs?
5/ What are the advantages and tradeoffs of using a Rogowanski coil vs conventional current transformers for current sensing?
6/ Will you consider the fault performance eg OC or SC load, or input supply transients?
Many thanks again for this most interesting and deep article.
Bon chance,
Jon -
I saw TI has an integrated (co-packaged?) driver + GaN FET they're advertising recently that does 150V/ns switching
Yeah, integrated driver-inverters are about the best you can do -- downside is you're limited to the conventional types. Current-sourcing inverters aren't particularly common, but they're nice when they are; any onboard bypass precludes that. (I think I've seen one or two that have onboard bypass? Offhand, I see the LMG5200 does not, so it could still be used in this way. Heh, but also in the datasheet, they show ringing, on what we can only presume is their recommended layout. So, well, there you go...)QuoteTo be clear, when discussing "eGaN" we're talking about discrete enhancement mode FETs using an GaN which generally seem to use a eHEMT construction right? I guess all the power GaN FETs that are in fashion right now are all eHEMT?
I'm referring to eGaN(R) by EPC, the, not-even-CSPs but actual dies with solder bumps.
But yeah, as far as I know they're all eHEMT GaN film on Si, or something like that.QuoteI might be looking at the problem wrong but for the power/current levels I'm looking at, ferrite core losses seem to be a limiting factor well before pushing into multi MHz territory.
Well, there's a few ferrites that might be useful up there, though I don't recall if you can even find e.g. planar shapes of them -- #61 and #67 (Fair-Rite, and similar types from others) would be a start, or even the classic RF powder types (Micrometals #2, etc.). And even air-core designs become feasible up there, though you'll probably get awful Qs from planar types.
Mind, power and frequency are inversely proportional -- this would be for small stuff like portable device chargers. There's not much reason -- or physical capability -- to run at say 10MHz and 1kW+ from a single inverter stage. At least not without a lot of dissipation (as ye olde RF amps did it).QuoteTwo (or more) steps ahead of me there with the synchronous rectification (SR). Still need to document (and in doing so double check) how input driving works and the ways in which ZVS seems to come apart as well as how well the first harmonic approximations carry to a more complete time-domain model. Haven't even really thought about how the secondary side tank is going to mess with SR but given there are multiple existing reference designs this hopefully won't be too much of a challenge...
Hmm. Might it pay to consider the network as a black box of some [complex] impedance, and call that a day? Certainly makes modeling easy...
I suspect it'll be a challenge to go directly from passive rectifier to active inverter: if you can match conduction angle perfectly, that's fine, but a devil to implement the control for. If you're planning on (mostly) continuous, full wave operation, that certainly won't pass -- and the network being a network, you fundamentally can't ignore what's going on at one end or the other, you must solve with both.
On the upside -- as long as it isn't saturating or anything, it should be perfectly justified to use superposition on it. That is, assuming one end is nearly shorted, what does the other end do, and vice versa? -- notice the inverters have nearly zero AC impedance, so act like dynamic short circuits.
Ah yes, so that will give quite a different response from the passive-rectified LLC -- in that case, the resonant frequency varies with load, and the gain can be quite high or low as the case may be, since the conduction angle varies, and effectively the load varies from Cr + Ls + R_L to Cr + R_L || (Ls + Lm).
With regards to dead time and ZVS, you of course have to sum the result from both sources -- ZVS is a nonlinear criteria so cannot be understood in terms of just one or just the other source.
Also, note that the inverter impedances aren't quite zero, because in addition to Rds(on) and ESL, there's a small compliance due to the switching edge itself, whether it swings very fast or somewhat slower (but not really slow, as that's the condition you wish to avoid by control, of course!). Indeed, a resonant tank of nominal impedance, strung between two nearly-short-circuit sources, will gladly draw as much current as you wish to pump into it!
I wonder if it ends up that you can have one inverter as primary control, and the other tracking, perhaps in terms of phase shift, perhaps to servo tank voltage or current? A phase shift PWM controller might be very useful here, though with a different control scheme than the square-pulse variety.
Which, I also have a test platform I can play with that on:
https://www.seventransistorlabs.com/Images/PSPWMFC_Layout.png
It's a primary side H-bridge (top-right) (preferably offline voltage, including filtering (top-left)), plenty of pads for coupling networks (middle), a nice compact and powerful RM12 transformer footprint (bottom-left), and push-pull synchronous or FWB passive (or maybe H-bridge synchronous with some hacking) secondary side rectifier/inverter (bottom left and mid), preferably low voltage but with enough spacing that it could be used at higher voltages too. On top of which, a discrete PSPWM controller (bottom-right, stacker board), since there are very few indeed of those out there, and I didn't see any to my liking for testing. And also aux supply and feedback stuff for convenience. And gate drive transformers because why not.
Tim -
Thank you for your input Jon! I was hoping you'd have a look.
Apologies for the formatting and readability, I've tried my best with the available BBCode tools but suggestions are welcome.
1. I did a large spreadsheet survey of available FETs including SiC and GaN FETs with a figure-of-merit calculated on approximate power loss:
\[P_{MOSFET} = \frac{1}{2} I_{D(RMS)}^2 R_{D(on)}+ \frac{1}{2}V_{DS} I_{D} (T_{rise}+T_{fall}) f_{sw}+ \frac{1}{2} V_{DS}^2 C_{oss} f_{sw}+ Q_{G} V_{GS} f_{sw}\]
The finding was that for this lower voltage implementation, plain Si is actually best! Even for my higher voltage system (>300V), the very best Si is on par or beats many SiC and GaN parts whilst having considerably lower costs. Some SiC and GaN parts can beat out Si but the marginal benefit does not seem worth the cost premium unless I go to yet higher frequencies and voltages. I am basing this assessment off datasheet values however.
2. Epcos (now within TDK), Ferroxcube and Fair-Rite are all in business and producing cores as well as new materials to my fairly recent knowledge. PC200 and PC50 are two that I also came across in my search however PC200 doesn't seem available off-the-shelf in the required size and PC50 doesn't seem available at all. I'm in Australia so I'm not sure MH&W will be easy to work with. I might take a look at trying to get my hands on some when I go to the production design unless someone could help me get my hands on some now? PC200 also seems to be recommended for an operating frequency well above mine (0.7 Mhz - 4 MHz), at those frequencies I have concern that resistive loss in windings will be difficult to manage due to skin/proximity effects and the high current levels and then there are added difficulties in driving, control and EMI. Most reference designs of this topology and power level seem to operate <1 MHz. There could be some poor assumptions here though so I'd love to be corrected.
Also on the topic of ferrite material selection. Something I'm not 100% certain about is potential issues trying to use higher frequency rated ferrites below their recommended range. As I understand \$f\times \hat{B}_{max}\$ (based on thermal limit tests generally using a toroidal core driven with a sinusoidal current) is a figure of merit for cores materials and each material has a peak about some frequency so operating the material significantly below (or above) that peak is likely to result in sub-optimal efficiency where an alternative material would be better. However, there are cross overs e.g. PC200 appears to have higher performance on the upper end of PC50 in that overview you've linked. In this overlapping region, are there other factors to consider? Higher frequency materials seem to generally have lower permeability so I presume higher leakage would be one downside? Higher costs could be another point though with my relatively limited survey of off-the-shelf cores so far the costs seem all over the place with even same shape and material core not having a strict correlation to material volume.
3. I have included IEEE in my searches but few seem of particular relevance yet to my level of investigation. I'll be sure to have a look for some of Dr Redl's papers. Admittedly, I've been tending towards surface level skimming of papers with a preference to first-hand analysis and simulation so far. I've found video lectures by Sam Ben-Yaakov (https://www.youtube.com/user/sambenyaakov) to be particularly helpful so far. My current bibliography is woefully incomplete in terms of papers I have collected (and only partially read).
4. Good question, I'll insert this answer into the OP too. Please do check if I'm making any errors.
PWM topologies:
Some of the other options available are PWM based conversion topologies i.e. buck-boost types (including SEPIC, Cuk, flyback), push-pull, non-resonant half bridge and non-resonant full bridge.
All these PWM options are non-resonant thus do not provide soft-switching or zero-voltage-switching (ZVS) i.e. they are hard-switching. This means the transistors used for switching are turned on under significant applied voltage. This is an issue because parasitic capacitance across the transistor causes charge to build up across the transistor with applied voltage which at turn-on is dumped through the transistor resulting to lost energy as heat and EMI. This is particularly an issue then operating at very high frequencies and voltages where this turn-on loss becomes a significant limit to system performance.
The buck-boost type topologies also rely on significant energy stored in an inductor to perform conversion which places extra demand on the magnetics used with higher DC flux and larger flux swings which tend to result in larger overall magnetics requirements and magnetics losses. By comparison, push-pull, half-bridge and full-bridge "true" transformer (not flyback mutual inductor "transformer") based topologies primarily use direct \$\frac{d\Phi}{dt}\$ flux swing coupling to perform conversion which means both flux and flux swings tend to be lower making them more suitable for higher current applications.
Buck-boost type topologies apart from flybacks are also not galvanically isolated which is potentially a safety issue in some applications.
Alternative resonant topologies are: Series resonant, Parallel Resonant, LLC and CCL.
These topologies and their variant forms use some form of resonant tank to which the output is coupled via a transformer. By performing switching across a resonant/reactive tank, switching can be coordinated such that turn-on occurs during zero voltage across the transistor. The difficulty with such topologies is that regulation of output is more complex, typically relying on frequency modulation in order to modulate impedances whilst maintaining ZVS. Between these different flavours of resonant topology, there are some different characteristics such as their response loads and frequency but among them LLC is known to be able to be tuned to have the most useful response. Sam Ben-Yaakov has a excellent video lecture on the topic here:
CLLC is simply a modification of LLC with added secondary series capacitance in order to produce symmetry.
On reminding myself of the different resonant topology characteristics: the component values used and the simulation results both in my presented design (so far) as well as some reference designs, the ratio of parallel/magnetising inductance to series inductance as well as the selected operating frequency is such that the system is tending towards degenerating to a series resonant topology. So I might go back and fix some values.
The potential for advanced, mixed-frequency/phase/PWM control systems using modern DSP is also opening up flexibility and performance of such topologies.
A fairly detailed albeit not exhaustive overview of switch mode topologies with their advantages and disadvantages can be found here:
M. Kamil "Switch Mode Power Supply (SMPS) Topologies (Part I)" AN1114, Microchip Technology, 2007, http://ww1.microchip.com/downloads/en/appnotes/01114a.pdf
Note on CLLC vs CLLLC:
The topology presented and analysed by me here I think should technically be called CLLLC but terminology in the literature is inconsistent. I came across this PhD dissertation today which makes a clear distinction between the two https://vtechworks.lib.vt.edu/handle/10919/77686. However, if you search for CLLC you'll find many papers presenting and discussing circuits with a discretely modelled LC secondary tank. So far CLLC seems to be more commonly used to describe the circuit so I'm going with that term.
5. It seems the TI reference design TIDM-02002 uses aRogowanskRogowski coil rather than a current transformer due to phase delay induced by the magnetic response of a CT core. https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/907393?tisearch=e2e-sitesearch&keymatch=TIDM-02002
6. I've considered we'll certainly need to do some fault handling for safety and reliability. Transients shouldn't be a huge issue due to the DC input (Batteries/PSU) and DC load (batteries and resistors for testing), soft start seems fairly simple using HF then ramping down though I do recall seeing one paper discussing potential issues during soft start and using phase shift/PWM for soft start... -
I've been out of the converter design loop for a few years now, but at one point I had spent some time with resonant and high frequency designs. But, I can comment on the devices, having spent the last decade looking at SiC and GaN power devices.
All the low voltage, commercially available GaN devices intended for power conversion are enhancement-mode HEMTs on a silicon substrate. There are some depletion-mode devices available, but the latter are for RF amps where they tolerate such nonsense
.
They do not have a PN junction, so they do not have a body diode in the usual sense, but they all act as a body diode when the gate is connected to the source (via gate drive or some other means). They are essentially turning themselves on in the reverse direction, so the voltage drop is the threshold plus whatever extra voltage is needed to conduct the current, usually about 2.5-3V. It is higher than a SI PN junction. However, there are a couple mitigating factors. First, there is no reverse recovery. This may not matter for a resonant converter operating at nominal load, but if you have to run at light load, or during startup, it may become very difficult to completely avoid hard switching, and you can end up spending a lot of time getting this to work as desired. Since reverse recovery losses can dominate total switching loss, this can be an important advantage.
Note that the lack of a PN junction is also the reason that GaN power FETs do not have an avalanche rating. The breakdown voltage is often much higher than the voltage rating, but it is wise to follow the spec and not exceed it, because it affects the lifetime of the part (exceeding the rating causes a gradual increase in on-state resistance).
While the low voltage GaN FETs tend to have lower output charge Qoss, we are talking 10s of percent lower vs Si. The gate charge might be 5-10x lower, and if you are running at a MHz, this has an impact on total losses. Housekeeping power is often an afterthought, but it can be a real headache if you at looking at efficiencies in the upper 90s.
The GaN Systems part has a package, and the gate can tolerate a higher voltage. This certainly makes the life of the layout engineer easier, and the higher voltage rating on the gate is a little more forgiving. The package adds size and inductance, though the added inductance very small. The chip-scale package of the EPC parts requires more attention to layout of the power loop and handling, but you can get a 7 mohm, 100V part for $0.90 in 1k quantities (Digikey pricing).
Disclaimer: I work for a GaN semiconductor company.
Cheers,
John -
I suspect it'll be a challenge to go directly from passive rectifier to active inverter: if you can match conduction angle perfectly, that's fine, but a devil to implement the control for. If you're planning on (mostly) continuous, full wave operation, that certainly won't pass -- and the network being a network, you fundamentally can't ignore what's going on at one end or the other, you must solve with both.
Not 100% clear what you're saying. You also seem to be using different names for the resonant capacitors and inductors and it's also not clear to me if you're talking about the ones on the input size or the output side?
On the upside -- as long as it isn't saturating or anything, it should be perfectly justified to use superposition on it. That is, assuming one end is nearly shorted, what does the other end do, and vice versa? -- notice the inverters have nearly zero AC impedance, so act like dynamic short circuits.
Ah yes, so that will give quite a different response from the passive-rectified LLC -- in that case, the resonant frequency varies with load, and the gain can be quite high or low as the case may be, since the conduction angle varies, and effectively the load varies from Cr + Ls + R_L to Cr + R_L || (Ls + Lm).
Though I think I see what you're saying more or less. I've observed in time domain simulations that as frequency and load changes when operating away from primary resonance so does phase difference between input inverter switching and output current. Looking at the previously derived value for output voltage across the resistive load (and hence output current)
\[M = \frac{X_m R_{ac}'}{X_m X_p + X_s'(X_m+X_p)+R_{ac}'(X_m+X_p)}\]
That \$X_s'(X_m+X_p)\$ term (together with the \$X_m\$ in the numerator) will add some imaginary component and the \$R_{ac}'(X_m+X_p)\$ will also add some real component which together will affect output current phase with respect to the input. So we'll see variation in that phase offset (conduction angle?) with changes to frequency (changes in reactances) and changes in load except for those special \$X_p=X_s' \rightarrow 0\$ and \$X_p +X_m \rightarrow 0\$ cases also previously analysed. You can also see this in the previously attached AC simulation graph for Vout.
The phase (dotted lines) change with load (different coloured lines) apart from at those special "resonance" points at 300kHz, 90.7kHz and then there that extra point I'm not sure about at 65.7kHz
For LLC analysis, you can simply set \$X_s'=0\$ and the equations will degenerate to those for LLC.
In the TI reference design TIDM-02002, their solution to this inconsistent output phase seems to be to sense output current and turn on the FETs according to detected current. Though there are some potential issues with response time and back feeding in certain conditions I think. In other reference designs and papers it isn't clear to me how they're doing synchronous rectification control or if they're doing it at all. -
Sandal, Thanks for the discussion.
At post #12 item 1 , did you have to manually enter the 5 parameters from various manufacturer's data sheets?
I was working with the high current fast capsule thyristors and diodes.
Westcode (now part of Littelfuse) handles the total loss calcs by publishing "ABCD" parameters for user computations.
It would be useful if there was an industry standard.
Ixys, for example only publishes p-spice parameters fro a limited range of components.
I use Quc-s and have not had much success using spice models in power electronics yet. I just use generics.
By the way the test current transformer is named after Walter Rogowski ( Not Rogowanski).
I have Rogowski here made by PEM (UK) It is RCTi-6 rated 5 kA 2 kV , the loop will close around a 100mm wide conductor
Bandwidth 0.6 Hz to 1 MHz.
By wrapping a 10 turn primary around it, it can measure down to about 1 Amp.
Although, I have not tried it above 100 kHz like that. -
Thanks for the input John. Good to hear from someone in the GaN business.
All the low voltage, commercially available GaN devices intended for power conversion are enhancement-mode HEMTs on a silicon substrate. There are some depletion-mode devices available, but the latter are for RF amps where they tolerate such nonsense
It that to say there are "high voltage" GaN devices out there which are not HEMTs?.They do not have a PN junction, so they do not have a body diode in the usual sense, but they all act as a body diode when the gate is connected to the source (via gate drive or some other means). They are essentially turning themselves on in the reverse direction, so the voltage drop is the threshold plus whatever extra voltage is needed to conduct the current, usually about 2.5-3V. It is higher than a SI PN junction. However, there are a couple mitigating factors. First, there is no reverse recovery. This may not matter for a resonant converter operating at nominal load, but if you have to run at light load, or during startup, it may become very difficult to completely avoid hard switching, and you can end up spending a lot of time getting this to work as desired. Since reverse recovery losses can dominate total switching loss, this can be an important advantage.
I'll have to be sure to capture and get some characterisation on this low load reverse recovery loss.
And additionally some good advice on GaN FET use. I'll need to add those EPC devices to my transistor survey.
-
Hello mag_therm thanks for the comments
At post #12 item 1 , did you have to manually enter the 5 parameters from various manufacturer's data sheets?
I did indeed manually scrape parameters from a great many datasheets and entered values into a spreadsheet though I actually ignored the \$\frac{1}{2}V_{DS} I_D (T_{rise}+T_{fall}) f_{sw}\$ term on the basis that \$T_{rise}+T_{fall}\$ will be controlled separately. However, with the variance in gate capacitances across the range of MOSFETs that's probably not a great assumption as some MOSFETs will be fundamentally limited on \$T_{rise}+T_{fall}\$ but at the same time those devices tend to get thrown out in the FOM (figure of merit) due to the other capacitive switching loss terms already. It does also assume hard switching which is also not entirely applicable for this application in a ZVS resonant converter so it's probably not a perfect FOM performance predictor but hopefully it's a bit more representative compared to some of the others out there.
It would be great if there was an industry standard but given how much different operating conditions affect performance it seems a bit hard to focus it down to a simple value any more than current datasheet values used in the FOM which are in themselves also approximation of actual physical characteristics. I saw some papers discussing different MOSFET FOMs and they didn't seem to have a great conclusion as far as getting something useful in application.
As for Pspice models its quite a mixed bag though most of the more modern and high performance stuff seems to have available Pspice models from the manufacturers. One of my reasons for choosing the TK46A08N1 was a available and functional Pspice model in addition to rough tying for best "overall" cost-performance and being available.
And thanks for that pick up on the typo. I've corrected it. Designing and implementing a Rogowski coil looks like a bit more trouble than I'd like so I might look for an alternative when we get to the synchronous rectification design stage. -
It that to say there are "high voltage" GaN devices out there which are not HEMTs?
I think all commercial GaN FETs in the 600V range are HEMTs or close. The core device technology is a lateral GaN device on a silicon substrate. By close, there is one technology that may be different, namely Panasonic's gate injection transistors, which look a lot like HEMTs structurally, but actually have some substantial gate current requirements, i.e. the gate is not purely capacitive. This requires a special gate drive. Infineon licenses at least some of Panasonic's technology, and I think they have a special driver IC.
Other 600V GaN devices actually use a depletion mode device in a cascode circuit with a low voltage silicon MOSFET. This makes the drive look like a MOSFET, but there are a lot of difficult issues to make this truly transparent to the end user. Transphorm, ViSiC amd perhaps TI use this approach, and United Silicon Carbide does something similar with a SiC JFET. The depletion mode GaN FETs were still HEMTs, last time I checked.
There is research on vertical GaN HEMTs and MOSFETs, in bulk GaN. These are mostly in the kV range, and none are commercial that I am aware of. Theoretically, they can be better and have an advantage at high voltage, but bulk GaN makes SiC look cheap.
John -
Not 100% clear what you're saying. You also seem to be using different names for the resonant capacitors and inductors and it's also not clear to me if you're talking about the ones on the input size or the output side?
LLC -- so only one C, the primary side, Cr.
Conduction angle: the amount of time the diodes are conducting. A choke-input rectifier has 100% conduction angle (well, as angle, 180 degrees per diode, 360 overall), a cap-input rectifier (or choke-input below critical current) has less, sometimes much less (high C, low L, Rsrc), which for mains purposes gives a very spiky current waveform, and quite poor PF.
We aren't worried about the harmonics or anything, but the conduction angle is related to dead time at the rectifier, and by extension, we can think of the synchronous rectifier's conduction angle as inverse of its dead time.
Inspecting this setup would be most closely related: https://www.eevblog.com/forum/projects/1kw-resonant-converter-analysis-design-build-and-validation/?action=dlattach;attach=1121292;image
Perhaps, adding a differential sense across the bridge to see what it's doing, and also vary load resistance and/or voltage?QuoteIn the TI reference design TIDM-02002, their solution to this inconsistent output phase seems to be to sense output current and turn on the FETs according to detected current. Though there are some potential issues with response time and back feeding in certain conditions I think. In other reference designs and papers it isn't clear to me how they're doing synchronous rectification control or if they're doing it at all.
Hmm, heh, one advantage to that is, if current is always swinging around, well, you can always wait until it swings positive (with respect to the currently active device), and ensure ZVS commutation that way (well, mostly, maybe). Downside, what if that current swing never happens? It deadlocks... So some other states should have to be added to ensure it keeps going, I think. Which may simply be part of light-load or low-conduction-angle conditions, and if so then that'll be pretty comprehensive I think. And there's nothing wrong with not activating the sync. rect. at all under those conditions, just let the body diodes do it passively*.
*Well, maybe. The recovery time will kind of suck in the high voltage version. At low voltages, it won't be much of a problem.
**Heh, y'know, reverse recovery is just staying on until current reverses -- its own enforcement of ZVS. Clearly, junction diodes know something!
Tim -
Inspecting this setup would be most closely related: https://www.eevblog.com/forum/projects/1kw-resonant-converter-analysis-design-build-and-validation/?action=dlattach;attach=1121292;image
I'll be sure to grab some captures of rectifier bridge conduction behaviour. It should help with understanding what synchronous rectification will need to look like.
Perhaps, adding a differential sense across the bridge to see what it's doing, and also vary load resistance and/or voltage?Hmm, heh, one advantage to that is, if current is always swinging around, well, you can always wait until it swings positive (with respect to the currently active device), and ensure ZVS commutation that way (well, mostly, maybe). Downside, what if that current swing never happens? It deadlocks...
Some synchronous rectified reference designs I've seen do as you say here and lock synchronous rectification off for light loads https://www.infineon.com/dgdl/Infineon-Evaluationboard_EVAL_3KW_2LLC_C7_20-ApplicationNotes-v01_00-EN.pdf?fileId=5546d462580663ef01582eb629b70118 (one of the better reference designs) pg. 39-40 So some other states should have to be added to ensure it keeps going, I think. Which may simply be part of light-load or low-conduction-angle conditions, and if so then that'll be pretty comprehensive I think. And there's nothing wrong with not activating the sync. rect. at all under those conditions, just let the body diodes do it passively*.*Well, maybe. The recovery time will kind of suck in the high voltage version. At low voltages, it won't be much of a problem.
Something I've also seen in reference designs warning against using Si instead of SiC devices in a synchronous rectifier because the reverse recovery in Si apparently causes reliability issues although I think that was in something written by a SiC vendor. I can't seem to find the exact paper...
Will need to keep that in mind when doing the higher voltage version.
-
*Well, maybe. The recovery time will kind of suck in the high voltage version. At low voltages, it won't be much of a problem.
**Heh, y'know, reverse recovery is just staying on until current reverses -- its own enforcement of ZVS. Clearly, junction diodes know something!
Tim
I would not neglect MOSFET body diode reverse recovery, even at low voltage. I would not believe any datasheet numbers on it, either. When you are aiming for 97% efficiency, they can be a big chunk of your loss budget. The "FETky" was invented to solve a problem.
Also, just being nit-picky, but reverse recover is staying on *after* the current reverses in the diode, so that reverse current flows. In many cases, this results in a shoot-through condition while the excess carriers in the junction recombine or are swept out.
Cheers,
John -
I would not neglect MOSFET body diode reverse recovery, even at low voltage. I would not believe any datasheet numbers on it, either. When you are aiming for 97% efficiency, they can be a big chunk of your loss budget. The "FETky" was invented to solve a problem.
I might add a survey of Schottky diodes to my list and grab some, then I can test and compare the performance differences too. I've seen an LLC using a Schottky rectified output which achieves 98.11% peak efficiency, the Wolfspeed CRD-06600DD065N 6.6 kW High Frequency DC-DC Converter https://www.wolfspeed.com/power/products/reference-designs/crd-06600dd065n
How accurate is reverse recovery modelling in LTspice models? I might need to do some testing, sims vs real life. I guess it's also going to be temperature dependent? Though I don't see datasheet curves or values for Qrr at temperature. -
Hi Sandal,
I have read through 3/4 of your posts.
This topology is very similar to my experience except yours is to be bidirectional.
Your series inductors do not include the Q factor. I would expect that to be in your loops.
That is, Rs1 and Rs2 in series with each of jwL1 and jwl2 respectively
Where Rs = jwL/Q_factor_inductor : see below for w
The efficiency with high voltage supply will be dominantly R2/ ( R2+Rs1+Rs2+R_other)
Did you consider this in the 95% efficiency specification?
On post #14, the series inductance is ( 0.7 uH * 2) and series capacitance is (400 nF/2) which give a resonant frequency of 300 kHz.
I assume from your source function that you are only using phase control.
At resonance , XL = j2.6 Ohm
This inverter's current will peak at around 300 kHz at approximately 50 Volt/Rload.
I think your green and blue traces are showing that.
If you include the series Rs values, the inverter will run happily at short circuit (R2=0) through resonance although the capacitor voltage will go high. and the inverter current may go too high for the semiconductors..
As R2 increases, the peak capacitor voltage will reduce, and the bandwith of the response vs frequency will widen
( BW = Fc/Q_factor )
As R2 increases too much, the inverter will no longer be able to control by phase control alone. ( But leave that till later.) Also the available output power will fall away.
These inverters will also run at 1/5 th and 1/3 of F-res_tank, as your 3 traces show.
This is usually undesirable, both for the control and for the commutation.
So I suggest to limit the F_sweep function ( your fsw) to about 200 kHz minimum so the lower peaks don't cause confusion.
Regards -
I might add a survey of Schottky diodes to my list and grab some, then I can test and compare the performance differences too. I've seen an LLC using a Schottky rectified output which achieves 98.11% peak efficiency, the Wolfspeed CRD-06600DD065N 6.6 kW High Frequency DC-DC Converter https://www.wolfspeed.com/power/products/reference-designs/crd-06600dd065n
How accurate is reverse recovery modelling in LTspice models? I might need to do some testing, sims vs real life. I guess it's also going to be temperature dependent? Though I don't see datasheet curves or values for Qrr at temperature.
I'm quite impressed with them. It's hard to appreciate how much recovery loss you're stuck with, in a UF5404 or what have you, until you pop in a schottky and it runs perfectly cool, despite the higher Vf. (Disclaimer: I haven't made any high voltage, high power supplies that actually pushed ratings on these things. I have bad enough luck just using single PN diodes -- let alone series chains of them -- in smaller (~100W) supplies...
)
SPICE recovery modeling: is awful. It doesn't capture the dynamic voltage (especially forward recovery), tends to underestimate recovery time, and losses; and certainly cannot capture the subtle behavior in pulsed operation (which involves bulk diffusion transport). At least the latter case only matters in pathological cases (short on-times, like for poorly dimensioned snubbers?).
Which is behavior worth mentioning, since it's not often documented -- when you forward-bias a diode very briefly, then immediately reverse it, the forward voltage can be quite large (e.g., 10s of V for a high speed diode and 1000 A/us -- and yes, this voltage is separable from the inductive EMF due to lead length and such), the reverse recovery time can be fairly short, and in particular the recovery softness can completely disappear.
The effect is exaggerated in general purpose (slow recovery) diodes (carrier lifetime is long, so that dense pockets of charge dissipate over ~us rather than 10s or 100s ns), and in high voltage diodes (where the depletion region is wide and very lightly doped, giving the same sort of effect as above).
Diodes optimized for this effect are called drift step recovery diodes, and can generate picosecond pulses. One instrument engineer I know of, found CRT line output transistors (the ~1500V 10A BJT kind) to have particularly useful behavior, creating a 1kV, couple ns pulse into 50 ohms.
As on-time increases, the charge in the junction reaches steady state (including nominal Vf), and reverse recovery is as expected (duration, peak and softness).
If softness is given in the datasheet, it can be approximated in the same way MOSFET switching losses can: assuming a linear voltage rise with constant or linear current fall. The actual response follows a curve, and of course depends on node capacitance and all that, so this is the same ballpark sort of approximation.
Another characteristic of recovery, is dynamic recovery: you can imagine, as time goes on, at first only a narrow part of the junction becomes depleted, therefore the voltage rating (avalanche threshold) is momentarily lower. Indeed, current flowing into that gap dissipates power, real recovery losses. This is easiest demonstrated with HV switching BJTs, with an inductive load and not enough snubber capacitance: Vce rises along a ramp, eventually reaching Vcbo or Vceo (depending on base off-bias). The same happens to PN diodes, but usually only shows up when loop inductance is erroneously high. (SPICE doesn't model this either.)
In SPICE, with a diode hard-switched in a high inductance loop, you can at least see a bouncing-ball sort of transient, which is realistic.
Tim