1kW Resonant Converter - Analysis, Design, Build and Validation

[JohnG]

I would add that the basic Spice model for reverse recovery with the built-in diode model is incorrect. It models transit time only, but not any excess charge storage. This means that you get something that looks sort of like reverse recovery, but is not really accurate at all. Worse, it can generate unrealistic steps in current which play havoc with convergence.

LTSpice has added a few years ago a damping factor Vp for diodes, and this produces a much more realistic reverse recovery. The problem that there is no good set of instructions on figuring out the right value. The help file references an paper, and it's not much help either, though it does explain the problem and solution. Another solution is to use a diode subcircuit with a model like the Lauritzen-Ma model. I did this some years ago developing a model for SiC body diodes. It works pretty well, and you can even make the parameters temperature-dependent. This is important because reverse recovery depends a lot on temperature, and usually gets much worse as devices get hot. Also, it is tedious as hell to measure devices and derive parameters, at least for anything fast. That's why I like GaN FETs and SiC Schottky diodes - you don't have to worry about it.

I second Tim's experience with the Cree/Wolfspeed SiC Schottky's. I have run them in a 30 MHz rectifier and they keep working. They don't make sense at low voltage, because they still have a couple volts drop.

Finally, note that usually, most of the losses due to reverse recovery happen not in the part whose diode is recovering, but the other FET in the half-bridge.

John

[gae_31]

Great Topic!
Also take a look at BSZ520N15NS3 which has very low output capacitance.

How will you about designing the transformer? do you plan on using something like Finite Element Analysis ? at those frequencies the high frequency losses in the windings can be immense.
Especially near the airgap.

[sandalcandal]

Non-linear Time Domain Simulation
Full analytical solutions to the "complete" non-linear LLC circuit in the time-domain seem quite involved and I haven't seen any complete analysis of all 6 operational modes in a CLLC or LLC system though there are some papers with partial analysis. So likewise I might do some analysis of narrow non-linear time-domain cases (e.g. ZVS conditions) but otherwise I'm going to rely on LTspice simulation.

Square Wave Input - Rectified Output
Before getting dug into detailed analysis of time-domain waveforms and behaviours of a spice circuit modelling "real" components including input inverter switching behaviour and output rectifiers I wanted to have a look at the simplified non-linear model used as the basis for the linearised FHA (first/fundamental harmonic analysis) and see how the linearised behaviour compares to the non-linear model.


Here is the LTspice circuit. Almost exactly the simplified model CLLC introduced earlier but I've put in voltage source left at 0V which I can use to help simulate a battery later on. The input square wave is parametrised to allow easy .step simulation over the frequency range. There are also a bunch of .meas directives to obtain various operating point characteristics. I've attached the .asc file of the simulation.

A quick look at waveforms first as a sanity check to make sure the circuit is behaving as it should and there's no major modelling errors (again will do a detailed analysis of waveforms later).

Some initial instability as the output capacitor charges then a steady state.

A smaller time scale look at the waveforms over a steady state cycle, things look as expected at resonance as per waveforms shown in literature (also checked above and below resonance but leaving out screenshots to reduce clutter).

Actually checking the frequency response of the system using the .step directive now.

The screenshot shows the circuit, the stacked Vout waveforms of each simulated frequency and the .meas plots. Note duration of simulation and measurement directives have been increased from above to make sure all iterations can reach steady state.


Nonlinear time-domain sim vs AC sim: Rload = 18, Rac = 14.6


Nonlinear time-domain sim vs AC sim: Rload = 2.5, Rac = 2.02


Nonlinear time-domain sim vs AC sim: Rload = 1.33, Rac = 1.08

The nonlinear time domain simulation frequency response matches the AC simulation frequency response quite well when well above the the primary + transformer resonance. In particular, the Vout matches very closely apart from light load around primary + transformer resonance. Current values also match pretty closely in terms of peak values apart from light load around primary + transformer resonance again. The maximum peak capacitor voltage doesn't agree with the AC simulation even accounting for \$\sqrt{2}\$ factor to convert RMS to sinusoidal peak.

R_load (Ω)	R_ac (Ω)	AC RMS (V)	AC Peak (V)	Time-Doman Peak (V)
1.33	1.08	357.8	506.0	480
2.5	2.02	219.2	310.0	335
18	14.6	259.1	366.4	275

The observed discrepencies as well as agreements between the nonlinear time domain simulation and the AC simulation could be explained due to the way the models are setup. The FHA is setup with an RMS equivalent input and output which works well enough since the input and output in the "actual" time domain model are effectively "DC" constant magnitude voltage. The intermediate network values are sinusoidal near primary tank resonance and roughly sinusoidal above resonance but below resonance they become significantly nonsinusoidal and all the extra harmonic content likely causes behaviour to start to deviate significantly from the FHA.


Waveforms at primary + transformer resonance showing non-sinusoidal form

Additionally, there is a small bump in the resonant capacitor voltage and transformer magnetising current frequency response around ~180kHz and currently I have no clue what it is due to.

Phase of the secondary current (important to implementing syncronus rectififcation) is similarly fair close between the time-domain and AC sims near primary resonance but starts to deviate at lower frequencies and is completely different by primary + transformer resonance. There are also some "glitches" in the phase plot due to aliasing type effects in the way .meas was setup to measure zero crossing time and derive phase. Perhaps there is a better way of doing it?

[sandalcandal]

Footnote: Convergence and spice Diodes
I initially simulated some  waveforms of the resonant capacitor voltage using LTspice's default diode model for the bridge rectifier. Some sharp spikes in the capacitor voltage at the input square wave's transients were observed.


Resonant capacitor voltage V(in, N001) at resonance when using default diode in bridge rectifier at primary resonance

\
Resonant capacitor voltage V(in, N001) at resonance when using default diode in bridge rectifier at fsw = 200 kHz (left) and fsw = 500 kHz (right)

Checking some other operating frequencies, the spikes disappear. The spikes are possibly reverse recovery in bridge diodes getting reflected through without filtering by primary/secondary tanks since they are at resonance.

In order to check if the spike were "real" I set maximum time step to 1ns at fsw=300k but this caused convergence issues. Swapping the LTspice solver to "Alternate" and the default diode model to a simplified ideal model was required to have the sim converge reliably. As a result of the changing to the ideal diode, the spikes disappeaared both at default/automatic and 1ns maximum time step. I also tried using a random pre-installed Schottky diode model and the issues with convergence and spikes also disappeared but the pre-installed Schottky diodes have too low a breakdown voltage to test the system across the full frequency range. It seems plausible that the cause of the spikes and convergence issues is diode model issues as JohnG described.


Breakdown of Schottky diode at light load

[gae_31]

The lt spice normal/default diode have a very abrupt behavior. In my experience adding some value for epsilon and rev epsilon and some resistance as you did helps a lot with convergence and speed.
These values are zero by default.

[sandalcandal]

Sorry for the delayed responses to comments. I need to actually do work and get stuff done instead of responding to people all day :x

Thanks for taking a detailed look, mag_therm

This topology is very similar to my experience  except yours is to be bidirectional.
Your series inductors do not include the Q factor. I would expect that to be in your loops.
 That is,  Rs1 and Rs2 in series with each of jwL1 and jwl2 respectively
Where Rs = jwL/Q_factor_inductor : see below for w

The efficiency with high voltage supply will be dominantly R2/ ( R2+Rs1+Rs2+R_other)
Did you consider this in the 95% efficiency specification?

I haven't included ESR (or Q) of the inductors in modelling so far but reference designs and models in literature I've seen also seem to ignore it and exceed my target efficiency. I assume constructing inductors/transformers with negligible ESR at this application level isn't fundamental problem though I don't doubt it's something that will significant effort to tackle.

As for control. My plan is to go with frequency modulation which seems to be the standard in reference designs. Your observations and interpretations of system frequency response seem in line with what I'm seeing in literature and myself too. I think I might need to adjust tank and transformer values to tune the location, amplitude and width of the peaks before actual implementation. Still going through understanding general characteristics at the moment however so keeping with the same values for now.

Reference designs I've seen operate in the region down to just below primary resonance, slightly up the primary + transformer resonant peak slope and avoid the messiness at and below that primary + transformer resonance peak (at 90kHz in the currently modelled circuit). ZVS no longer occurs down at these frequencies anyway. So in this case, that means limiting fsw to about 200kHz minimum as you say.  Analysing the "full range" for now is still interesting and potentially useful in getting a more complete understanding of the circuit behaviour however.

[sandalcandal]

Great info on the diode modelling stuff Tim and John! Thanks!

I had a look at the Lauritzen-Ma model and it looks quite elegant. I'm not sure I can get comparable models or required parameters online though and I'm not sure setting up then going through the required characterisation will be possible within the current scope particularly being worthwhile in terms of the benefits it will bring. If I have to acquire the devices and whack them in some custom test rig then grab and process waveforms just to do more sims I'm not sure it'll be worth the resources compared to just whacking it in the actual circuit. I could be convinced otherwise if I can find an efficient way of getting these high accuracy models.

Alternatively, I could just use Schottky diodes as people seem to quite like. Adding them in addition to the secondary active bridge FETs could lead to some excessive cost however.

note that usually, most of the losses due to reverse recovery happen not in the part whose diode is recovering, but the other FET in the half-bridge.

Great note to make. The realised losses showing up in another component is quite counter intuitive.

[sandalcandal]

Thanks for the comments gae_31!

Great Topic!
Also take a look at BSZ520N15NS3 which has very low output capacitance.

How will you about designing the transformer? do you plan on using something like Finite Element Analysis ? at those frequencies the high frequency losses in the windings can be immense.
Especially near the airgap.

I had a squizz at the BSZ520N15NS3 and the output capacitance is very low indeed but the on-resistance is a bit high. For my operating conditions, the on-resistance losses are going to outweigh the capacitive switching losses and total losses will likely be higher overall if I use that MOSFET compared to the TK46A08N1 I have on hand now. The C_oss to R_DS(on) is ratio is fairly run of the mill for modern Si MOSFETs. Probably a good option if we were to operating at lower current and higher ~1Mhz frequency.

As for the transformer, I'll have a crack a designing my own using rough equations then FEA using FEMM and see how it goes. For the final actual product, I'm thinking of outsourcing that part of design to a specialty magnetics designer.

The lt spice normal/default diode have a very abrupt behavior. In my experience adding some value for epsilon and rev epsilon and some resistance as you did helps a lot with convergence and speed.
These values are zero by default.

Thanks for the tip  Hopefully it can help me limp through some uncooperative simulations.

[gae_31]

   
At Primary Resonance
\[I_{p(rp)} = \frac{V_{in}(R_{ac}'+X_m+X_s')}{X_m(X_s'+R_{ac}')} = \frac{V_{in}}{X_m||(X_s'+R_{ac}')}\]
The primary current is determined by the parallel impedance of the magnetising inductance and secondary side impedance as one would expect. Maintaining a higher magnetising inductance for the
transformer will ensure the tank current does not become excessive under no load (as with a normal transformer).

sandalcandal, I understand the math going on here, but I do not fully follow the reasoning and I want to make sure I am not missing anything. To my understanding the minimum tank current will occur at no load right ? so, I guess you want maintain a high magnetizing inductance just to limit the magnetizing current not necessarily for the tank current.
please correct me if I am wrong.

[gae_31]

Question 1
Inductance Required for Combined Coss Charging
ZVS in an LLC or CLLC circuit relies on inductive current being present in the primary tank and/or the transformer magnetising inductance such that when the input driving MOSFET pair is turned-off the inductive current will cause a reversal of voltage across the primary tank + transformer forcing reverse biasing of MOSFET body diodes (or "true" zero voltage if timing is perfect) in the alternate MOSFET pair before they are turned-on. This turn-off, reversal, turn-on cannot happen instantaneously due to a variety of factors including MOSFET output rise/fall time and importantly here, the need to charge/discharge MOSFET output capacitances, thus there needs to be a "dead time" period between initiating turn-off of one MOSFET pair and turn-on of the alternate MOSFET pair to allow time for the voltage reversal to occur.

\[L_{m(Cossmax)}< \frac{t_d}{16 C_{oss} f_{sw(max)}}\]
Not sure about the formula for \$L_{m(Cossmax)}\$ the maximum inductance allowed such that MOSFET output capacitance \$C_{oss}\$ can be charged within the dead time \${t_d}\$ so that ZVS is achieved. I can’t find a reference with the full derivation and there seems to be conflicting information in the literature. My closest derivation (which is the one shown above) is a factor of 2 higher than values shown in literature. The equation shown in literature is the same as above but is being provided for a half bridge circuit which is half the total effective capacitance to be charged i.e. for HB: Ceq=2Coss+Cstray but for FB: Ceq=4Coss+Cstray. The above is derived using peak magnetising current available to charge combined Coss at start of dead time.

For the “complete” non-linear time-domain picture of an LLC with full bridge input and full bridge rectified output, operating near primary tank resonance, the magnetising “inductor” of the transformer will see a square wave with amplitude \$n V_{out}=V_{in}\$ with a period \$ T_{sw} = \frac{1}{f_{sw}}\$. The magnetising inductor current \$I_m\$ will thus rise to a peak value just before switching and dead-time:
\[I_{m(pk)}=\frac{N V_{out}}{L_m}\frac{T_{sw}}{4} \text{(Current in inductor, constant voltage)}\]
Supposition: This will be the minimum current available available during dead time unless operating at extreme frequencies (relative resonance) [footnote 1]  This current must be able to discharge the output capacitances of the MOSFETs plus any additional stray capacitances within the dead-time in order to flip the voltage and achieve zero-voltage turn-on for the alternate MOSFET pair i.e. the charge delivered by the magnetising inductor current \$q_{m(d)}\$ during dead-time \$t_d\$ must be equal to or greater than the total charge of the MOSFET outputs and stray capacitances \$ q_{eq} \$.
\begin{align*}
q_{m(d)} &\geq q_{eq}\\
I_{m(pk)} t_{d} &\geq C_{eq} V_{in}
\end{align*}
Let \$C_{stray} = 0\$
\begin{align*}
\frac{N V_{out}}{L_m}\frac{T_{sw}}{4} t_{d} &\geq 4 C_{oss} V_{in}\\
L_{m} &\leq \frac{t_d T_{sw}}{16 C_{oss}}\\
L_{m(Cossmax)} &\leq \frac{t_d}{16 C_{oss} f_{sw(max)}}\\
\end{align*}
Again, for circuits where this is shown in literature, it is generally shown with a half bridge so \$C_{eq} = 2C_{oss}\$ instead and this derivation would yield.
\[L_{m(Cossmax)} \leq \frac{t_d}{8 C_{oss} f_{sw(max)}}\]
Thus there is a factor of 2 discrepancy.

There is another possible derivation which seems to be implied in the literature of a similar value where the condition is instead: the inductive energy of the transformer magnetising inductance \$E_L\$ must be greater than the capacitive energy of the MOSFET output capacitance \$E_C\$.
\[E_L = \frac{1}{2} L_m I_{m(pk)}^2 = \frac{V_{in}^2}{L_m}\frac{T_{sw}}{32}\]
\[E_C = \frac{1}{2} C_{eq} V_{in}^2 = 2 C_{oss} V_{in}^2\]
\begin{align*}
   E_L &\geq E_C \\
   \frac{V_{in}^2}{L_m}\frac{T_{sw}}{32} &\geq 2 C_{oss} V_{in}^2 \\
   L_{m} &\leq \frac{T_{sw}^2}{64 C_{oss}}
\end{align*}
Note there is no \$t_d\$ is this upper limit for \$L_m\$. For the previously derived equation for \$L_{m(Cossmax)}\$ to be equivalent, \$t_d = \frac{T_{sw}}{4}\$ and if the dead time is any shorter than one quarter switching period \$t_d<\frac{T_{sw}}{4}\$ (which is quite likely to be the case) then the previously defined \$L_{m(Cossmax)}\$ will be a tighter bound. So this upper limit of transformer magnetising inductance based on energy is not relevant.

Any idea on where I've made a mistake or the equation in literature comes from? Given there are at least some papers supporting my personally derived value I think I'm going to keep going with what I have for the time being and assume the literature contrary is wrong.
------------------------------------------------------------------------------------------------------------

$$V_{lm}=L\ast\frac{di}{dt}$$
Where the voltage across Lm = NVout during 0-T/2 :
$$I_{Lm,peak}=\frac{N\ast V_{out}\ast t}{L_m}$$
The peak current occurs during T/2 but the current in the inductor rises from -Ipeak to Ipeak during 0-T/2. so
$$I_{Lm,peak-to-peak}=\frac{N\ast V_{out}\ast\frac{T}{2}}{L_m}$$
Since Ipeak = 0.5 * Ipeak-Ipeak 
$$I_{Lm,peak}=\frac{N\ast V_{out}\ast\frac{T}{4}}{L_m}$$
So, assuming the winding capacitance = 0 and output capacitance is zero we find ,
$$I_c=c_{equivalent}\ast\frac{dV}{dt}$$
So for discharge :
$$I_c=I_{Lm,peak}$$
So for half bridge :
$$c_{equivalent}=2\ c_{oss}$$
$$I_c=2\ast\frac{V_{in}}{t_{dead}}\ast\ c_{oss}$$

So note now that for half bridge:
$$N=\frac{\frac{{V}_{{in}}}{\mathbf{2}}}{V_{out}}$$
Working out :
$$I_c=I_{Lm,peak}$$
$$\frac{N\ast V_{out}\ast\frac{T}{4}}{L_m}=2\ast\frac{V_{in}}{t_{dead}}\ast\ c_{oss}$$
$$\frac{\frac{\frac{Vin}{\mathbf{2}}}{V_{out}}\ast V_{out}\ast\frac{T}{4}}{L_m}=2\ast\frac{V_{in}}{t_{dead}}$$
$$L_m=\frac{T\ast t\ d\ e\ a\ d}{16\ast c_{oss}}$$

For the full bridge :
$$c_{equivalent}=4\ c_{oss}$$
But
$$N=\frac{V_{in}}{V_{out}}$$
so working that out would result in the same equation

[sandalcandal]

At Primary Resonance
\[I_{p(rp)} = \frac{V_{in}(R_{ac}'+X_m+X_s')}{X_m(X_s'+R_{ac}')} = \frac{V_{in}}{X_m||(X_s'+R_{ac}')}\]
The primary current is determined by the parallel impedance of the magnetising inductance and secondary side impedance as one would expect. Maintaining a higher magnetising inductance for the
transformer will ensure the tank current does not become excessive under no load (as with a normal transformer).

sandalcandal, I understand the math going on here, but I do not fully follow the reasoning and I want to make sure I am not missing anything. To my understanding the minimum tank current will occur at no load right ? so, I guess you want maintain a high magnetizing inductance just to limit the magnetizing current not necessarily for the tank current.
please correct me if I am wrong.

The actual minimum tank current over the frequency range of around primary resonance to primary + transformer resonance seems to depend highly on primary tank and transformer parameters as well as loading conditions (see numerical plots in the 2nd post). With the component values being used so far I think the minimum tank current is actually between the two resonances at high load (low Rac). My equations and derivations just look what the values are at the two resonant points. My derivations so far don't find or guarantee any one point is a maximum or minimum (but they do guarantee some phase characteristics in the FHA though this is less relevant or useful in the actual circuit).

Higher magnetising inductance lowers primary current (i.e. primary tank current) as well as magnetising current at the resonances according to my equations thus far. The note being made is that higher magnetising inductance is desirable in general as it seems to generally reduce the current through components. The numerical analysis in the 2nd post indicates that maxima occur at either primary or primary+transformer resonance however there is that mystery resonance/peak at ~65kHz and high loads which is greater than the other two known resonances in some cases. I don't have a complete analytical proof that increased magnetising inductance always results in lowered current levels but there's an observation that it generally seems to lower current levels.

I've attached the FHA LTspice file

For component value effects on magnetising current specifically, see the magnetising current equations which are a bit before the primary side current equations..

Edit: I posted then realised I have the answer and changed the following paragraph.
On that mystery resonance/peak at ~65kHz, it definitely seems to be some sort of actual resonance since the phase is stable with load and it seems to hold up in the time-domain simulations but I can't intuitively see what would be resonating at that low frequency. Logically it should be something like primary+secondary resonance or some sort of "whole circuit" resonance. Primary+secondary resonant frequency is the same as just primary resonant frequency because the primary and secondary tanks are matched so that leaves whole circuit resonance. Using symbolic solving in Mathematica, finding the "whole circuit" resonance \$ X_p + (X_m || X_s') = 0\$ gives an ugly set of equations but one of them numerically evaluates to 64.8 kHz which is about right.
\[\omega_{rWhole} = \sqrt{2} \sqrt{\frac{1}{-j \sqrt{-C_p^2 (L_m+L_p)^2+2 C_p  C_s \left(-L_m^2+L_m (L_p+L_s)+L_p  L_s\right)-C_s^2 L_m+L_s)^2}+C_p
   (L_m+L_p)+C_s (L_m+L_s)}}\]
I haven't done validation of the above equation beyond the above numerical substitution so it might not be correct. The actual circuit is also very unlikely to ever operate in this region so I'm leaving further investigation of this off for now in the interest of pushing ahead with a getting a practical circuit done but anyone else feel free to probe further. Edit: If one were to use burst mode operation for light load operation then one could conceivably excite one of these resonances (most importantly the primary+transformer resonance at light load) which would cause issues.

Low frequency mystery whole circuit resonance output voltage


Low frequency mystery whole circuit resonance magnetising current


Low frequency whole circuit resonance disappears when shorting/bypassing secondary tank


Edit: Additional impedance plot of whole circuit showing 3 resonance points.

...
so working that out would result in the same equation

On the Coss max inductance bound it looks like you've done pretty much the exact same derivation to me apart from me essentially skipping the I_pk-pk step and just directly using T/4 so makes sense we get the same result. I wonder if the contradicting papers just copied the formula from elsewhere without realising it is only for full bridge configurations. See gae_31's below post.

[gae_31]

Sandal, My derivation is for the half bridge.
Note the difference in the turn ratio “n” between the full bridge and half bridge.
This difference compensates the difference in Cequivalent, yielding the same equation.

[sandalcandal]

Sandal, My derivation is for the half bridge.
Note the difference in the turn ratio “n” between the full bridge and half bridge.
This difference compensates the difference in Cequivalent, yielding the same equation.

Ah yes, I see it now! Sorry, I was thinking about the low frequency resonance and glazed over your derivation's details. Thanks! That solves that problem. Excellent! 

I've edited my previous posts to link to your solution.

[gae_31]

Although not of importance, the peak at the lower frequency(65kHz) is bugging me.
Playing around with the math for complex impedances, shows sometimes some funny insights.
For example the paralllel impedance of the L2,C2 at 65 Khz with Lm is equal to approximately 5.6 I Ohm. Which is equal to a equivalent inductor of 14 uH.
What I find funny is that at low frequencies the total impedance of a L and C in parallel is greater than the single impedance of one 1, which is completely different from the non-complex world.
so basically it seems that this "artifical" 14uH inductor resonates with C1 and L1 at 65 Khz.



Anyway, thanks for the analysis on the magnetizing current, I finally have the time now to get through it. How are your progressing with the design ? looking forward to any updates  .

[T3sl4co1l]

That's (C1 || C2) + (L1 || L2) + Lm.  0.8uF and 7.35uH resonates at 65.6kHz.

This is easily seen if we move some things around, in particular consider the two sources as short circuits.  Due to symmetry, we can convert the two series branches (C1+L1+source 1, C2+L2+source 2) into a single parallel equivalent, from a single equivalent source.   Hence C1 and C2 act in parallel, and L1 and L2.  Since V1 is driving and R2 is zero (an implicit source of 0V), we can take their equivalent as |V1| / 2.  Which only affects the amplitude -- the dynamics are still there even with no source present.  So the parallel equivalent is correct, and the resonant frequency is given by the values above.

Mind that the exact equivalent will change as source and load amplitude and impedance are adjusted -- in particular, the diode rectifier will have a very different impedance, ranging from small capacitance (diode CJO) for very small signals (Vpk < Vf), or transient throttle-down conditions where the output voltage remains high (no diode conduction); to a dominantly resistive characteristic, somewhere near full load).  Whereas the synchronous rectifier behaves more like an inverter itself (i.e., a low impedance source).  (The sync. rect. could still be timed to give the dependent impedance of a bridge -- but more likely it will be driven full wave like the primary inverter, power transfer being determined by some combination of their driven frequency, or the phase shift between the two.)

Tim

[sandalcandal]

Sorry for the lack of updates. I was planning on documenting and posting some of the time-domain waveform behaviours but there isn't too much interesting there that isn't in well documented in literature already apart from conduction angle stuff which Tim has mentioned and becomes significant when trying to charge a battery near the output gain limit (maximum output voltage) of the converter so I should share those...

Work has been a bit slow with some other distractions and end-of-year slowness but currently the big problem I'm somewhat stuck on is deciding which MCU platform/family to go with for the DSP control. Its obviously a major part of the system and will require sinking some significant resources (mostly time learning the platform) to get things going which I assume will be largely non-transferable if things turn out to be sub-optimal or otherwise have issues. Time to working prototype is somewhat reduced by picking MCUs with available reference design LLC implementations or otherwise joining the bandwagon with popular MCUs where community support is more readily available but I'm not sure about locking in myself and any future engineers to such a decision without a strong fundamental analysis. I'm thinking about writing my thoughts and findings and posting another thread to get feedback and suggestions.

I've also been having a look at some isolated gate driver IC options.

That's (C1 || C2) + (L1 || L2) + Lm.  0.8uF and 7.35uH resonates at 65.6kHz.

This is easily seen if we move some things around, in particular consider the two sources as short circuits.  Due to symmetry, we can convert the two series branches (C1+L1+source 1, C2+L2+source 2) into a single parallel equivalent, from a single equivalent source.   Hence C1 and C2 act in parallel, and L1 and L2.  Since V1 is driving and R2 is zero (an implicit source of 0V), we can take their equivalent as |V1| / 2.  Which only affects the amplitude -- the dynamics are still there even with no source present.  So the parallel equivalent is correct, and the resonant frequency is given by the values above.

Mind that the exact equivalent will change as source and load amplitude and impedance are adjusted -- in particular, the diode rectifier will have a very different impedance, ranging from small capacitance (diode CJO) for very small signals (Vpk < Vf), or transient throttle-down conditions where the output voltage remains high (no diode conduction); to a dominantly resistive characteristic, somewhere near full load).  Whereas the synchronous rectifier behaves more like an inverter itself (i.e., a low impedance source).  (The sync. rect. could still be timed to give the dependent impedance of a bridge -- but more likely it will be driven full wave like the primary inverter, power transfer being determined by some combination of their driven frequency, or the phase shift between the two.)

Tim

Thanks for the insight Tim! That's a clever way of looking at the circuit.

Potential issues with low frequency resonances for burst mode operation
Initially, I was thinking the low frequency resonances could be completely ignored in the actual operation of the circuit but it came to mind that if one were to use burst mode operation for light load operation then one could conceivably excite one of these resonances (most importantly the primary+transformer resonance at light load) which would cause issues.

[gae_31]

For full digital control of pwm buck I have used dspic33 of microchip, which eventually worked fine for the project. I did struggle a lot with getting familiar with  all the conversions etc , probably because of my hardware background.
For future designs however, I want to use the TI chips, such as TMS320F28004x. They are bit more expensive, but on the other hand they have Floating point unit.
With fixed point arithmetic, when designing the control loop, it is much easier and less time consuming to use FPU than fixed point due to the issues of Fixed point such as rounding errors and the ease of changing the coefficients with making mistakes.

I also wonder, what you exactly want to do in the MCU? Do you want the full control loop inside?
Or do you also consider a hybrid solution, where the control is done analog but the references, housekeeping etc are done by the MCU?
I think it is indeed a good idea to start a seperate discussion on this and get the insights of the community.

[slloyd]

resonant capacitor selection is fairly straight forward for frequencies <300Khz. here the MKP metalized polypropelene capacitors work great.  look at your tank voltage, RMS, and then look at capacitor voltage vs. frequency chart. probably need to connect two capacitors in series to get the voltage. you need a few of them in parallel to get the current rating so i like to pick lower nF capacitor so i can add a bunch in parallel to reach the calculated value.

EPCOS B32651 for example.

I find it a lot harder with MLCC caps because they don't have the same handy voltage vs. frequency plots in datasheet. do you have any tips here?

otherwise, the only thing next to add to your analysis is the transformer & resonant inductor design (could be combined into one). i had all this transformer design done and went to a manufacturering house i've used for years, and they said the problem with all the ideal math is you just can't so easily get the ferrite you want in the time you want it in the low volume you desire. Also.. forget all the fancy core shapes.. design using ETD shape as its by far the cheapest.

anyway, some other (better) choices of ferrite cores for high frequency >500kHz
ML91 (which is better than PC63), Hitachi metals ML95 might be even better
Ferroxcube 3F36 which is better than ACME P61, TDK PC95, Ferrox 3F45 as shown on core loss vs. Flux density at 500khz

[slloyd]

also on subject of transformer design. the LLC, or CLLC, or CLLLC converter.. the math ends up specifying the magnetizing inductance and leakage inductance. its really hard to find a COTS transformer to fit, so i always ended up going custom design. but i wonder for the purpose of your experiment.. it would be better to start with a COTS transformer and work the math backwards to see what range of voltage and/or resonant frequency this transformer could be used.

[sandalcandal]

A general update to everyone, CLLC dev is still ongoing with my involvement but the actual work (apart from some magnetics design stuff) has been handed to another person so sharing the progress is a bit hard. We've also gone straight to our "final" voltage-power design so I can't really share the designs for that reason too. Hopefully I can give some high level summary stuff at the end and still have discussions about aspects though.

Thanks for the notes slloyd.

resonant capacitor selection is fairly straight forward for frequencies <300Khz. here the MKP metalized polypropelene capacitors work great.  look at your tank voltage, RMS, and then look at capacitor voltage vs. frequency chart. probably need to connect two capacitors in series to get the voltage. you need a few of them in parallel to get the current rating so i like to pick lower nF capacitor so i can add a bunch in parallel to reach the calculated value.

I'm still worried about long term temperature degradation for plastic film caps then also performance looks worse on paper and size is much worse for plastic film compared to MLCC of similar suitability. Power density and weight are really important for our application so we're going with MLCC still despite higher costs.

I find it a lot harder with MLCC caps because they don't have the same handy voltage vs. frequency plots in datasheet. do you have any tips here?

My understanding is MLCC doesn't have voltage vs. frequency derating like plastic film capacitors do due to the much lower dielectric loss, higher thermal conductivity and temperature tolerance of the ceramic dielectric so you just need to make sure peak voltage isn't exceed the rating and that's it. The main limitation to look out for seems to be more towards current-frequency-temperature rise. Most of the big manufacturers have detailed plots for current-frequency-temperature rise and lots of other characteristics but usually as a separate webpage or online database tool not part of the datasheet; though these tools are sometimes missing parts.
Murata: https://ds.murata.co.jp/simsurfing/index.html?lcid=en-us
Kemet: https://ksim3.kemet.com/
TDK database example: https://product.tdk.com/en/search/capacitor/ceramic/mlcc/info?part_no=CGA4J1C0G2A333J125AC

As for picking achievable magnetic parameters, that has been a bit of an iterative process with lots of "in-house" magnetics exploration. First looking at available cores then playing with them to find achievable parameters through calculations/simulation then feeding that back into the resonant design. Eventually ending up with a design that has efficiently/cheaply achievable magnetic requirements. Against the advice you got, I found the standard range of standard shapes and sizes allows pretty much any set of parameters you could want; the challenge is more picking the smallest possible core/material to achieve the requirements for minimum cost and weight (weight is important in our application).

I can confirm ETD is one of the better shapes so far as availability, cost effectiveness and performance. Round centre legs are good for efficient winding to achieve required inductances with minimum wire length and hence copper loss. I also note "pot" type cores such as P, PQ, PM and RM (PQ seems the worst of the bunch in most cases) seem to be more effective than E-variant cores.

Thanks for the notes on magnetic materials. For materials in our <500kHz application we are looking at Ferroxcube 3C97 as a preferred material due to loss characteristics and temperature range or Epcos N97 as a cheaper or at least more readily available alternative.

So far as going backwards from COTS transformers, I didn't see any that were near handling our power requirements but it seems like a decent idea for stuff with more conventional power requirements like an IT/computer PSU using LLC. Usually for COTS transformers they seem to have a predetermined reference design and IC associated with them so all this first principles detail level of design stuff seems kinda redundant.

Cheers

[sandalcandal]

Just realised I forgot to attach LTSpice sims for people to play with.

Edit: Also discussion on light load conditions here: https://www.eevblog.com/forum/projects/unloaded-llc-converter-will-it-keep-voltage-as-calculated/

[johnywhy]

there is a small bump in the resonant capacitor voltage and transformer magnetising current frequency response around ~180kHz and currently I have no clue what it is due to.

Did you solve that?

Thx!