Electronics > Projects, Designs, and Technical Stuff
1st try at SEPIC charger layout
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Tomorokoshi:
1. The Vsw and Vin nets off U1 look a bit scrawny.

2. Starting on page 8 of the datasheet it talks about the input capacitor. It starts out specifying a "low ESR 22μF, 25V solid tantalum capacitor" which then changes to a "2.2μF ceramic capacitor such as the one used for the coupling capacitor". I'm not quite sure what they're up to, but I recently had to deal with an LT SEPIC converter where I also used similar guidance provided by the datasheet. It would be nice if there was more explanation about such a big change.

I wasn't using their exact circuit. I turned the 2.2 uF input capacitor into the inside of a PI filter, with another 2.2 uF ceramic (see a theme here?) on the input, with a small inductor in between.

The design failed the Conducted Emissions EMC test, which was tracked down to discontinuous shutdown / restart operation of the switcher because of the runaway voltage drop at the input caused by the LISN impedance. My 2.2 uF inside ceramic capacitor, which at my nominal input voltage of 24 V was now derated to around 1 uF, was run down to a voltage low enough that the switcher would reset.

The solution was to replace the outside capacitor with a 47 uF electrolytic, and to upgrade the inside to a 10 uF ceramic.

I did verify that my PI filter wasn't the cause of my EMC issues with the LISN. The PI filter allows for bypassed DC power from the electrolytic, with the ceramic taking up the high speed switching. Best use of each type without trying to roll it all into a tantalum.
charliehorse55:
How well does the design handle voltage spikes? They are common in an automotive space - the input rails may easily see 100V+ during a load dump.

Ref. http://www.ti.com/lit/an/snva681a/snva681a.pdf
ratio:
The next try. A board shrink, we're now about 1-3/4" square. The power traces are 50 mils, the Saturn toolkit says that's good for over 3 amps, which should be fine. Ground pour on the top & bottom, not displayed. I moved a few parts to the back side to shorten up the high current path. This resulted in vias in the pads, but I figure that's not going to be a real issue with hand soldering.

After looking at it again, I think I might be too scant on clearances between the inductor and C3. I'll bring in the components & lay it out on a printed sheet to dry fit everything before I send the board out.
SiliconWizard:
Using via-in-pad, even if you're strictly going to use this board for hand-soldering, may still cause you some issues. Quite a few PCB manufacturers may frown upon this and force you to have plugged vias (which can be expensive) otherwise that would violate their DRC. Especially the low-cost ones which usually don't waste more than a couple minutes validating a PCB design before sending it to production...
ratio:
Thanks for the heads up. The uploader at OSH Park didn't seem to mind, they show up clearly in the rendered view. I suppose they might not make a complete DRC pass this early in the process though, I guess a call to support is indicated.
This is just a personal project, I can't currently imagine a need for more than one or two of them.
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