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2 stage OpAmp

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kingkings:
 

hello guys , i have been designing 2 stage Op Amp with this specs

and this is what i have done so far

 



my input voltage here is 1 V , i know i should decrease it because my supply is 3V , but to what value so i can saturate my mosfets and get the 75dB

Wimberleytech:
Is it stable?
What is the phase margin?
Did it meet you SR spec?
You are burning a lot of current in the input stage...why?

Your gain depends on gm and r0, where r0 depends on channel-length-modulation...determined by your model.  Where are you getting your model?  Level 1,2,3, ?? 
Looks like a Cadence schematic...would be nice if you simulated it in LTSpice and provided an asc file.

As a starting point the ratio of Pm0/Pm1 should be twice Nm4/Nm0:  Pm0/Pm1= 2*2/6 = 4/6 NE 6/10...but close I guess.

Jay_Diddy_B:
Hi Wimberlytech and the group,

I have modelled lots of circuits in LTspice, but never tried IC design. I know that this can be done, I have heard that Linear Tech used LTspice for many of their IC designs.

I followed instruction that I found here:

http://www.blog-tm.de/?p=291

And inserted the PTM from here:

http://ptm.asu.edu/modelcard/2006/65nm_bulk.pm

I assume that this is the NMOS and PMOS models for 65nm process.

I used the W parameter to vary the geometry between the MOSFETs and built a 1:12 current mirror:



This gives M2 drain current is 1.2mA  (not the desired result)


Do I have set other parameters?



I assume that you need a PTM for the process that you are using?

The LTspice License agreement includes:

4. Restrictions. Licensee shall not ...

Snip ..

 This program is specifically not licensed for use by semiconductor manufacturers in the design, promotion, demonstration, development, or sale of their products. Specific permission must be obtained from Analog Devices for the use of LTspice for these applications.


I guess it is okay for educational use.

Regards,
Jay_Diddy_B

 Current Mirror.asc (5.91 kB - downloaded 48 times.)

Jay_Diddy_B:
Hi,

There are other process models here:

http://ptm.asu.edu/latest.html

If I switch my LTspice model to use the 90nm BSIM3 I get a bunch of warnings but I get M2 Drain current 124uA which is better.

Model attached below.

Regards,

Jay_Diddy_B
 Current Mirror 90nm.asc (8.71 kB - downloaded 47 times.)

Wimberleytech:

--- Quote from: Jay_Diddy_B on May 25, 2020, 02:29:51 am ---Hi Wimberlytech and the group,

I have modelled lots of circuits in LTspice, but never tried IC design. I know that this can be done, I have heard that Linear Tech used LTspice for many of their IC designs.

I followed instruction that I found here:

http://www.blog-tm.de/?p=291

And inserted the PTM from here:

http://ptm.asu.edu/modelcard/2006/65nm_bulk.pm

I assume that this is the NMOS and PMOS models for 65nm process.

I used the W parameter to vary the geometry between the MOSFETs and built a 1:12 current mirror:

(Attachment Link)

This gives M2 drain current is 1.2mA  (not the desired result)


Do I have set other parameters?


Regards,
Jay_Diddy_B


--- End quote ---
I have never used Level 54 model.  However, if this is a 65nm process, your voltages are too high.  I ran some curve tracer simulations using the model and it is clear that you need to keep voltages below about 1.2 volts.  But, there is still gate current...I question the model, frankly

You are not setting you channel length.  Not sure what LTSpice defaults to.  You need to set W=xx L=xx

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