| Electronics > Projects, Designs, and Technical Stuff |
| 20 bit up/down counter, anything more elegant than a bunch of cascaded 4516's? |
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| SiliconWizard:
There's the 74LS491 which is 10-bit, but available nowhere except brokers. Not cheap either. I've found some for about $5 each, but this is clearly not a viable solution if you need regular supply. I've also found the SN74LV8154 which is interesting but doesn't seem to do down-counting, and the counter register(s) are available through some kind of MUX, so that may not be practical for your application if you need all 20 bits at once. Haven't found/or don't know of any other current and available IC for your requirements. Is this going to be a product? If so, frankly, a small CPLD would likely be the cheapest and best long-term solution, and depending on the other logic parts in your design, may even allow you to significantly reduce the parts number. If you're uncomfortable programming one, I'm sure people here can give you source code for it (a few lines of code should do the trick) and programming tool's cost shouldn't be an issue at all. If it's going to be only a prototype (or a few of them), then I'm not sure I see the problem with parts that are around $5 or even $10 (yes very expensive for what they do, but the time you used for finding alternate solutions is probably worth a lot more 8) ). |
| kony:
XC9572XL. Few lines of verilog, almost fully remappable pinout, under a 1$/pc even in small qty and with space to spare for other glue logic still. Or any other flavour of CPLD. |
| edavid:
--- Quote from: kony on December 31, 2018, 04:23:00 pm ---XC9572XL. Few lines of verilog, almost fully remappable pinout, under a 1$/pc even in small qty and with space to spare for other glue logic still. Or any other flavour of CPLD. --- End quote --- For those who have experience with these CPLDs, how many macrocells does it take to implement an up/down counter stage? |
| NiHaoMike:
--- Quote from: edavid on December 31, 2018, 05:10:58 pm --- --- Quote from: kony on December 31, 2018, 04:23:00 pm ---XC9572XL. Few lines of verilog, almost fully remappable pinout, under a 1$/pc even in small qty and with space to spare for other glue logic still. Or any other flavour of CPLD. --- End quote --- For those who have experience with these CPLDs, how many macrocells does it take to implement an up/down counter stage? --- End quote --- Download the free version of ISE and try compiling a design yourself. |
| kony:
Just did it for a hell of it - gated up/down counter with synchronnous reset is 20 marcocells (that is less than 30% of the resources of the XC9572XL). |
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