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Electronics => Projects, Designs, and Technical Stuff => Topic started by: Custom on March 03, 2016, 06:07:00 pm

Title: 24 bit dc volt meter design
Post by: Custom on March 03, 2016, 06:07:00 pm
 I'm about to begin designing my next project, a 24 bit dc voltage / current meter. I would like a few different ranges to maximize the adc's resolution. I don't need high voltage readings, I'm more wanting a meter that gets into nanovolts.
Ranges:
40.000.0v
4.000.000v
0.400.000.0mV
0.040.000.00mV
0.004.000.000mV

Question 1: what is the best way to switch through ranges like that. I know the 40v is just divider w/ chopper amp buffer, 4v just chopper amp buffer. The lower ranges though, do I make a non inverting amp with decade resistor setup or should I switch the adc's reference? I was going to be using a high precision 4.096v or 2.048v, whichever makes sense.

Question 2: the switching device, should I use relays, analog switch / mux ic, or a rotor switch? There will be a micro in play of course so if I'm missing any options.

No schematics or diagrams right now just thinking high level at the moment. Thanks for any suggestions and answers. This is a great community and love that I can share things like this.
Title: Re: 24 bit dc volt meter design
Post by: Alfons on March 03, 2016, 06:43:20 pm
Here you can pick up some ideas. I have not built the circuit:

http://www.heise.de/ct/artikel/Messwerkeln-291398.html (http://www.heise.de/ct/artikel/Messwerkeln-291398.html)

http://www.thoralt.de/wiki/index.php/DIV (http://www.thoralt.de/wiki/index.php/DIV)
Title: Re: 24 bit dc volt meter design
Post by: Kleinstein on March 03, 2016, 08:28:59 pm
The 40 V range will be divider - buffer - ADC. The 4 V range might work as just buffer - ADC, but here it depends on the ADC what range it can use just a buffer. The lower ranges will likely have an non inverting amplifier stage as the input - amplifier. Switching the reference of the ADC is not a common way, as it only makes sense for a limited range like 1:2 - so not a big help for a high resolution ADC.

For the input amplifier you have essentially two options: using a ready made AZ OP, or using some kind of autozero switching and a low noise FET amplifier. With AZ OPs there is a trade of between noise and bias currents.

For the switches, semiconductor switches like CMOS MUX chips or JFETs tend to have lower DC error, but higher leakage compared to relays. For less than +-15 V the CMOS MUX chips is usually the best choice, if some leakage can be tolerated. Good JFETs can be better with leakage, but are more complicated to use.  There is also Photomos as an alternative to a relay.
So it might end up as a combination of relay (or photo-mos) for the 40 V part, JFETs at the input (if needed) and CMOS for changing amplification.

An important decision is also the degree of input protection, as this will also add noise and possibly leakage.
Title: Re: 24 bit dc volt meter design
Post by: acbern on March 04, 2016, 09:29:01 am
So you want to make a 4µV input range, <0.1ppm resolution meter?? What accuracy? The references you think about have probably a factor of 100 more in drift per K. Just the references, all analog stuff adds. Also the ADC (assume you intend to use a standard audio ADC, nothing homemade) is drifty. Measuring 4µV with the best test gear available is not fun.
There is a good reason why the 34420A only has 1mV lowest range. You should be very happy if you can reach a factor of 10 in resolution and noise of that meter, and less in accuracy (and maybe that or less is even what you intend, it is not clear). It will be extremely tough to even do that, this starts with the input cables (everything pure copper, meaning custom binding posts, no plating, solder will be an issue in the frontend area), goes on with the relays (must be avoided in this branch, the best I know have 30nV of thermal offset (which is hard to compensate, but you probably cannot buy them anyway, custom, and the worse is its drifts), to mention just a few.
So you should initially define what you want to achive (resolution, accuracy, noise, bandwidth).
As a starting point as literature I would recommend The Art of Electronics and the 34420 schematics.
 
Title: Re: 24 bit dc volt meter design
Post by: Custom on March 12, 2016, 01:38:12 pm
That is incorrect acbern, i'm going for 4mV full scale but after more thinking I believe that 40mV full scale will be plenty, that would take me into the 10 ppm range i think. I can see what you mean when I look back at how I wrote the ranges. I havent really tried to spec an exact accuracy, really just going for as good as i can get kinda thing.

Kleinstein, when you speak of "photomos", is that the same thing as a solid state relay?

I have come up with a block diagram of the inputs and adc with some part #s i have been looking at. Could this wonderful group of engineers take a look at this and let me know if im on the right track, or if I will encounter some major issues or not. Thanks again
Title: Re: 24 bit dc volt meter design
Post by: Kleinstein on March 12, 2016, 02:53:38 pm
The CMOS switch at the input will not work, as it will still see the "high" voltage. Also leakage current of CMOS switches tends to be on the high side, at least the guaranteed value. Usually there is no need for a separate divider for a 40 V and 75 V range. Just a single divider is usually enough. Its not the absolute best noise wise to go from 40 V down to 2 V and than amplify back to 4 V, but it's usually acceptable. One could also ues a 10 V range and than first have an buffer and a divider after that - there are OPs to handle +-10 V as well.  Also the divider can be higher impedance - a 200 K impedance only works with very low resistance sources. So the divider is usually at 10 M or maybe 1 M.

One also has to consider input protection, e.g. at least to protect the input against ESD and something like caps charged to 100-300 V or so.

For the current ranges, there also should be some protection - usually fuse and diodes. Also I would avoid mechanical switches / relays as much as possible, as they can have quite some thermal EMF. The usual way is to have the shunts in series and switch the load current to the right point. The voltage is measured from the end of the chain. For the shunts the steps with 4 A and 4 mA are rather large as this would mean quite some noise at the low end and a high drop at the upper end. For low currents (e.g. < 4 mA) the use of a TIA might be a good idea.
Title: Re: 24 bit dc volt meter design
Post by: TimFox on March 12, 2016, 03:07:38 pm
What input resistance do you want at 4 V and below full-scale ranges?
Title: Re: 24 bit dc volt meter design
Post by: Kleinstein on March 12, 2016, 05:04:39 pm
For the low ranges one usually likes to have a really high input impedance, like that what the OPs and input protection / switching allows. So something like more than 10 GOhms, the higher the better. The exact value might depend on surface leakage, humidity and dirt on the board. Besides the resistance also input current should be small, e.g. well below 1 nA. One may have to find a balance between low leakage and low noise.

Typically the input needs a switch / relay to disconnect the direct path to the amplifier for the low ranges. This switch needs to withstand the full voltage so either a good relay or MOSFETs with photoelectric control  (e.g. like in the Keithley 2000 and similar) or similar as integrated photo-mos IC, a kind of DC solid state relays.

Also a switch for the the input divider for the high voltages is needed, to allow for the high impedance. Here there is the option to have the switch at the low side, as the switch is open only at low voltage ranges. However a relay at the divider would not really matter that much as a few µV of EMF is not that critical in the 20 V or higher ranges. The relay would allow to choose a lower input impedance (e.g. 10 M) as an option for the low ranges, though seldom needed. I would go for a relay, as this an easy way to get very good isolation.
Title: Re: 24 bit dc volt meter design
Post by: branadic on March 12, 2016, 05:11:35 pm
Seems similar to what a Keithley 181 Nanovoltmeter is about, smallest range is 2mV. It contains a LM399, as far as the datasheet indicates. Maybe you want to have a look on their schematics?
Title: Re: 24 bit dc volt meter design
Post by: Custom on March 16, 2016, 02:55:11 pm
I definitely see the issue with the High voltage being at the low voltage switch, thats fixed. Also removed the separate dividers, just a 100v range. After doing that i realized that the 4v range isnt really high enough so i would much rather change that to a 10v range but what would the benefit be by placing the buffer before the divider? is that to drive up the input impedance?

I definitely need a higher input impedance and for the low ranges, i would like it to be like 2GOhms but how does that get implemented? just 2 GOhm resistor in series with the low ranges? And I notice professional units usually have a switch between 10 M and 2 G, what is the 10 M impedance needed for and would I need that for a DC only meter?

I have been looking at different cmos analog switches, photomos isolators, and optomos solid state relays and cmos switches have the lowest leakage current by far, typically 500pA - 1nA. the optomos / photomos is 50 - 500 nA typ. to 1uA. Not sure if im looking at the best parts though.

I do have plans to put some input protection. Probably a MOV and clamping diodes. and for current, a fuse and opposing diodes to clamp voltage to .6 volts.

Will update diagram to reflect changes. Thanks again
 
Title: Re: 24 bit dc volt meter design
Post by: Morgoroth on March 16, 2016, 03:14:43 pm
This may help

https://www.dropbox.com/s/93vweu3lb2ynlyj/Keithley-LowLevelHandbook_7Ed.pdf (https://www.dropbox.com/s/93vweu3lb2ynlyj/Keithley-LowLevelHandbook_7Ed.pdf)

Title: Re: 24 bit dc volt meter design
Post by: Kleinstein on March 16, 2016, 04:14:33 pm
The advantage of having the buffer for something like a 10 V range before the divider is that the divider can be lower impedance and thus lower noise. A divider with 9 M and 1 M has quite some noise, possibly more than you like. Also the input impedance can be much higher, like in the low ranges.

The input impedance is usually something like 10 M from the divider, or just the input impedance of the amplifier / protection elements. So the high impedance is not well defined, and the specs are more like more than 1 or 10 G Ohm, but the actually impedance might well be in the 100 G range and can be nonlinear / temperature dependent. There is usually not much sense to add something like 1 G to GND just to get a more constant, but than lower impedance.

I might be a good idea to look at a few input circuits of commercial DMMs.

For protection usually clamping diode towards bootstrapped zener diodes is a good choice. So normally the diode see essentially zero voltage (only the amplifiers offset). The amplifier is usually need to drive guard lines anyway.

For the switches, the difficulty is that often the leakage is only specified as an upper limit - typical leakage can be much lower. So meters may use selected parts, e.g. otherwise normal parts but checked to meet tighter specs. The leakage also depends on the voltage, getting higher at the limits.
Usually JFETs can be a little better when it comes to leakage than CMOS, at least at low voltages. However control is more complicated.