Electronics > Projects, Designs, and Technical Stuff
3 stages power amplifier project
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dmills:

--- Quote from: magic on December 19, 2019, 08:24:55 am ---I don't think you need to cascode jfets just to make them work. And besides, OP has no spec on noise and offset voltage so what's the problem with BJT ;)

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Yea, used to designs with WAY higher supply rails where the cascode really helps with the available choice of fet.

I was instinctively sweating the output offset, but your right there is only half a spec.
Also, whats with the weirdly low open loop gain? Assuming that is a DC value I would expect something about three orders of magnitude higher, but then I likes my current mirror loads and emitter follower Vas.

Regards, Dan.
Lucky-Luka:

--- Quote from: dmills on December 18, 2019, 11:22:40 pm ---Add about 0.33 ohms in the emitter leads of the final power devices, and a few tens of ohms between the emitters of the driver transistors (Helps the horrifically slow finals turn off).

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Do you see this slowness in the simulation?
Keep in mind that this is just a simulation project for an analog electronics course at the university and that this is my first project of a power amplifier. I know that you are telling me how to make it perform better in real life but I just needed to keep it as simple as possible to accomplish the task needed.


--- Quote from: dmills on December 18, 2019, 11:22:40 pm ---Given the general crapness of the '3055, I might be tempted to go for an EF triple just to try go get the load on the Vas down to something more reasonable, even if you are going for an EF Vas, but with 14V required on a 16V rail that is a bit tricky, might have to use a CFP instead.

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Can I say that I haven't understood anything?  :'(



--- Quote from: dmills on December 18, 2019, 11:22:40 pm ---Wind up the bias until you have about 30mV across one of the emitter resistors.

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Why 30mV?

Thanks
Lucky-Luka:

--- Quote from: dmills on December 19, 2019, 01:31:34 am ---open loop gain at what frequency?

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I have to check


--- Quote from: dmills on December 19, 2019, 01:31:34 am ---THD at what frequency?

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Not specified


--- Quote from: dmills on December 19, 2019, 01:31:34 am ---Is 80kHz full power bandwidth or something more reasonable, what is the slew rate requirement?

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Not specified


--- Quote from: dmills on December 19, 2019, 01:31:34 am ---That efficiency is at full power output?

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Yes


--- Quote from: dmills on December 19, 2019, 01:31:34 am ---Are cascoded jfets allowed for the input pair? Makes hitting that 10k input Z a bit easier.

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No, since the subject wasn't touched during the course.


--- Quote from: dmills on December 19, 2019, 01:31:34 am ---By three stage I assume the lecturer means input LTP, Vas and output stage?

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Differential pair + CE + EF
dmills:
Get thee to a library, borrow a copy of "Designing audio power amplifiers" by Bob Cordell, or "Design of audio power amplifiers" by Douglas Self.

Everything you need to know is there.

Given the craptacular choice of BJTs offered in LtSpice I might be very temped to do the parallel thing to get sufficient current rating and power dissipation out of some of the smaller but less 'historical' parts they actually offer.

Lucky-Luka:

--- Quote from: Zero999 on December 18, 2019, 11:35:56 pm ---I've tweaked the VBE multiplier until the bias current in the output stage was reasonable.

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Have you noticed my bias current was way too high? :)
Which is a reasonable value? You have more or less 35mA. Is there a rule of thumb?
After that current is decided, did you choose the right voltage across the Vbe multiplier?
Thanks
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