There is something deeply wrong with LT spices model of at least some of those transistors, because for shits and giggles I drew a fairly conventional power amp, and at a gain of 80, the miserable thing was stable with NO compensation cap at all!
Now granted a gain of 80 is more then slightly problematic if you want 80kHz BW with that choice of output sand, so I dropped the gain to 20, still allegedly stable.... Just seems very, very unlikely.
Playing with it, I don't think the obvious EF output stage is easily going to get you there, not quite enough voltage headroom by the time you include the emitter resistors and the current source/Vas transistors. I suspect you are going to need to bite the bullet and design with the load in the collector circuit.
Your spec is also seriously incomplete, open loop gain at what frequency? THD at what frequency? Is 80kHz full power bandwidth or something more reasonable, what is the slew rate requirement? That efficiency is at full power output?
Are cascoded jfets allowed for the input pair? Makes hitting that 10k input Z a bit easier.
By three stage I assume the lecturer means input LTP, Vas and output stage?