Electronics > Projects, Designs, and Technical Stuff
3rd order Sallen Key Unity Gain LPF - stability question
JDW:
I have been testing a 3rd order Sallen Key LPF on a breadboard and so far have not had problems, but I am curious about the potential for instability and oscillation. My existing design acts as a LPF but also a low source impedance input to an ADC pin on my PIC MCU. That is important since the maximum recommended impedance on ADC inputs on my PIC is 10k-ohm. I used the following online calculator to create the LPF design:
http://sim.okawa-denshi.jp/en/Sallenkey3Lowkeisan.htm
R1 = R2 = R3 = 330k-ohm
C1 = C2 = 1nF
C3 = 480pF
fc1 = 482.29Hz
My chosen Op-Amp is a Microchip MCP601:
https://www.mouser.jp/datasheet/2/268/21314f-29012.pdf
Here's a partial schematic:
The input comes from a car at R1 & R4. Specifically, there's an audio keypad on the steering wheel of many Toyota cars that let's you adjust Volume and Seek. When those buttons on the steering wheel are pressed, you get the voltages shown at right in my schematic. The voltages are fixed voltage for as long as the state shown persists, and the voltages seem to come from a resistor voltage-divided on the car side, with a maximum resistance of 3k-ohm. I am using my PIC16F1503's ADC input to read the voltage level via my LPF so my PIC knows what button is being pressed.
As you can see in the okawa-denshi calculator above, the component values I used do not oscillate. However, if I were to plug in different resistance values within a 5% tolerance, I sometimes get shown an oscillation frequency. 5% resistors are cheaper than 1%, which has me thinking about oscillation.
FYI, I am using large value resistors because the input impedance of the OP AMP is very high and can easily accommodate that. Also, using larger resistances allows me to use smaller capacitors, which is highly desirable for a shorter capacitor discharge time, which allows for a shorter ADC acquisition time.
All said, I am curious to hear thoughts about the stability of my design over the tolerance range of the parts chosen on my schematic and whether it would be safe to use 5% tolerance resistors.
Thank you.
Wimberleytech:
Did you adhere the instructions on proximity of bypass capacitor? Also, did you include an additional 1uF within 100mm?
Can you show us your board or circuit hookup?
JDW:
--- Quote from: Wimberleytech on April 24, 2020, 06:01:52 pm ---Did you adhere the instructions on proximity of bypass capacitor? Also, did you include an additional 1uF within 100mm?
Can you show us your board or circuit hookup?
--- End quote ---
I certainly appreciate your reply, but I'm a little confused by what you wrote. As I said, I have found NOTHING WRONG in my BREADBOARD testing of the circuit shown in my schematic. And as you can see in my schematic, I have a 0.1uF bypass capacitor (C4) on Vdd. And of course it is in close proximity to the Vdd pin. There is no instability at all IN MY TESTING. But I don't know if such will be the case as temperature changes have an impact on resistance values (within their tolerance, of course).
The reason I posted is because I don't have extensive experience in FILTER DESIGN, and certainly not a 3rd order Low Pass using an op amp. I generated the design with that Japanese web page generator. The design seems to work fine in my testing on a breadboard, but my main concern is to ensure my current design will not oscillate as component values change within their tolerance range. My schematic currently shows 1% tolerance resistors, but I am inclined to use 5% tolerance resistors for reasons of cost. (Yes, even pennies matter.) But when I plug in different resistance values, all within a 5% tolerance, into that Japanese LPF calculator, there are some instances where the calculator shows an oscillation frequency. I take that to mean there would be some instability if resistance values were not exactly what my schematic shows. Maybe I am wrong in assuming that, I don't know. Again, that is why I posted here to find out.
All said, I would appreciate hearing from someone experienced in LPF design, especially someone who understands the intricacies of a 3rd order LP Sallen Key filter such as the one presented in my schematic.
Thank you!
nctnico:
I'd use a 2 pole Sallen-Key filter and put an RC filter on the side of the ADC. This will shield the opamp from the ADC's capacitive sampling. Whether or not a Sallen-Key filter is prone to oscillation (peaking) depends on the steepness of the filter or better put: the phase margin. There might be better calculators out there which also let you specifiy the phase margin.
Why is D1 there? If it is for over voltage protection then leave it out. First of all: never dump overvoltage into the supply rail. Secondly the input protection ESD diodes should be able to deal with any overvoltage situation since there is a 660k Ohm resistor in series (and the capacitor helps to get rid of spikes).
Wimberleytech:
--- Quote from: JDW on April 24, 2020, 11:36:43 pm ---
--- Quote from: Wimberleytech on April 24, 2020, 06:01:52 pm ---Did you adhere the instructions on proximity of bypass capacitor? Also, did you include an additional 1uF within 100mm?
Can you show us your board or circuit hookup?
--- End quote ---
I certainly appreciate your reply, but I'm a little confused by what you wrote. As I said, I have found NOTHING WRONG in my BREADBOARD testing of the circuit shown in my schematic. And as you can see in my schematic, I have a 0.1uF bypass capacitor (C4) on Vdd. And of course it is in close proximity to the Vdd pin. There is no instability at all IN MY TESTING. But I don't know if such will be the case as temperature changes have an impact on resistance values (within their tolerance, of course).
The reason I posted is because I don't have extensive experience in FILTER DESIGN, and certainly not a 3rd order Low Pass using an op amp. I generated the design with that Japanese web page generator. The design seems to work fine in my testing on a breadboard, but my main concern is to ensure my current design will not oscillate as component values change within their tolerance range. My schematic currently shows 1% tolerance resistors, but I am inclined to use 5% tolerance resistors for reasons of cost. (Yes, even pennies matter.) But when I plug in different resistance values, all within a 5% tolerance, into that Japanese LPF calculator, there are some instances where the calculator shows an oscillation frequency. I take that to mean there would be some instability if resistance values were not exactly what my schematic shows. Maybe I am wrong in assuming that, I don't know. Again, that is why I posted here to find out.
All said, I would appreciate hearing from someone experienced in LPF design, especially someone who understands the intricacies of a 3rd order LP Sallen Key filter such as the one presented in my schematic.
Thank you!
--- End quote ---
First, did you read the excerpt from the datasheet that I posted?
I am pretty sure that your filter is not oscillating due to 5% variance in resistors. But, lets just say that I wrong.
What is the frequency of oscillation? Can you show us an oscilloscope trace?
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