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4 channel ADC, 10 MHz, 8 bit design
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Kleinstein:
The positive input voltage would better be derived from the ADCs reference voltage, even if it takes another buffer.

A fuse at the input might be a good idea if the zerner protection is used. Otherwise it would nor help much - ESD would not blow even a 10 mA very fast fuse, unless dangerously high.

Depending on the resistor size, it might be a good idea to have the input resistor with 2 or 3 resistors in series to give it a higher withstanding voltage. Depending on the maximum frequency needed one might sill need small caps parallel to the resistors that set the gain. With only 150 K it is a lot lower impedance - so one might just get away without. With a 150 K resistor at the input (but without the zeners), this could be good enough to withstand mains voltage - at least if there are no mayor spikes. So I am not a big fan of the zeners at the input. I would more prefer something like a MOV and maybe a fusible resistor if really needed.
splin:

--- Quote from: FrankBuss on November 29, 2018, 07:47:12 am ---But with the positive reference I think VRTS will be better than the +5V, because it is USB powered, and can be very noisy and getting low like 4.8 V depending on cable quality etc., and would be nice if it would be at least maybe 0.2 V accurate. But I added some 0 ohm resistors, will try it on the prototype, if it works when VRB is connected to GND. And if VRTS is not good enough, I can bodge some voltage regulator at this input as well on the prototype. Attached is the next version.
--- End quote ---

VRTS is just a resistor to Vdd so it will be just as noisy as Vdd. It would be a good idea to provide a reference even if it is a cheap regulator or a TL431 (< $.1) with a couple of resistors. That way you can get reasonable performance - it's never going to be a precision data aquisition module with only 8 bits - but it may be useful for other purposes. But do be careful to note this from the datasheet:


--- Quote ---No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits  driving the CLK, OE, analog input and reference pins do not come up any faster than does the voltage at the ADC1175 power pins.
--- End quote ---

That shouldn't be a problem at power-on since 5V will be up first but at power down, depending on the amount of capacitance on the 5V rail compared to Vref, it's possible for Vref to hold up longer than Vdd - ie. don't put much capacitance on Vref in an attempt to make it as quiet as possible.

Also don't forget that the input bandwidth is ill-defined, depending on the capacitance across the feedback resistor. With 2pF, LTSpice shows the BW as 2.2MHz with the inverting configuration, but a few pF variance due to board layout, component parasitics etc will dramatically alter the BW. The capacitance wil be hard to measure directly so I guess you'll have to use a signal source and examine the ADC o/p to determine the actual BW.
FrankBuss:
I don't think that I need a MOV or more protection, it is just for a little bit protection if I connect it to higher voltages, but not mains. But I changed the input resistor to 1206, should be good enough even for mains in combination with the fuse and the diode at the input. It is not a standard zener diode, but a TVS diode, this one, should be safe.

Attached is a new version of the schematic. I used this voltage regulator for the VRT input, optionally selectable with 0 ohm resistors. 4 V should give enough headroom with the low drop regulator, even for very low USB voltages. I also added some test points and cleaned up the circuit diagram, I think this might be the final version, at least for the first prototype and to measure something.
FrankBuss:

--- Quote from: splin on November 29, 2018, 10:54:56 pm ---
--- Quote ---No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits  driving the CLK, OE, analog input and reference pins do not come up any faster than does the voltage at the ADC1175 power pins.
--- End quote ---

That shouldn't be a problem at power-on since 5V will be up first but at power down, depending on the amount of capacitance on the 5V rail compared to Vref, it's possible for Vref to hold up longer than Vdd - ie. don't put much capacitance on Vref in an attempt to make it as quiet as possible.

--- End quote ---

The sample circuits on page 16 and 17 uses 10 uF capacitors for the reference inputs, and all powered from the same 5V supply. But I guess 1 uF might be sufficient and then no problem when powering down.

But I wonder why there is this warning in the datasheet. What worst can happen, if the voltage on VRT is higher from a small 10 uF capacitor for a short time? I guess all it would do is flowing into the VDD supply through the internal resistor, in case of the self-biasing cirucit, and if used disconnected from VRTS, then maybe flowing through some internal protection diodes to VDD. Shouldn't damage the chip.
StillTrying:
On the last pdf the inverting and non-inverting inputs are reversed.
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