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| 4 channel ADC, 10 MHz, 8 bit design |
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| Kleinstein:
--- Quote from: FrankBuss on November 30, 2018, 06:24:37 pm ---...... The sample circuits on page 16 and 17 uses 10 uF capacitors for the reference inputs, and all powered from the same 5V supply. But I guess 1 uF might be sufficient and then no problem when powering down. But I wonder why there is this warning in the datasheet. What worst can happen, if the voltage on VRT is higher from a small 10 uF capacitor for a short time? I guess all it would do is flowing into the VDD supply through the internal resistor, in case of the self-biasing cirucit, and if used disconnected from VRTS, then maybe flowing through some internal protection diodes to VDD. Shouldn't damage the chip. --- End quote --- The problem with a voltage higher than the supply, it that the protective diodes at the pins are actually kind of gates of parasitic thyristors. It only take enough current for a short time to trigger a latch up. It depends on the chip how much current is needed. That extra warning might be there because the chip might be a little sensitive. The point that saves the day is that there are no other parts at the supply that can bring drown the 4/5 V supply fast. This kind of limits the current on the VDD side. The worst case would be some short, fast dropout at VDD (e.g. someone connecting an empty 1000 µF cap). |
| FrankBuss:
Ok, attached is a new version of the ADC. I think it is not a good idea to make the ADC-in pin available at the pin header, and the OpAmp is corrected, and some additional pins for measuring the current consumption are added. I think now I can start with the layout. And the Arduino shield form-factor base board is attached. I used this clock driver, because I decided to allow up to 8 ADC modules, and might be a bit too much load for the FPGA pin output for a clean clock signal. To minimize the pin count for the output enable pin, I used this de-mux. I couldn't find any information about how it behaves when switching. Is it break-before-make? I guess it is not that important, because would be only a very short time, but a break-before-make behavior would be good to minimize spikes, if multiple ADC module data outputs are driving the bus at the same time. |
| FrankBuss:
I don't think I can do the high sampling rate with just 8 data pins. Initially I planned to use the OE pin and query all 4 channels between samples. But the required setup and hold times and the strange 2.5 clock pipeline delay, would make this very critical for 4 channels, and impossible for 8 channels. I could add some high speed buffers, but I decided to use a DE10 Nano, which has enough GPIO pins to sample 8 channel all in parallel. This is the main board: https://github.com/FrankBuss/adc4/blob/master/kicad/adc/adc.pdf And this is one channel: https://github.com/FrankBuss/adc4/blob/master/kicad/adc/adc1-ADC1.pdf I also changed the ADC1175 to the ADC1175-50, which can sample with up to 50 MHz, and doesn't cost much more. I guess I would need to reduce C5 then for a higher analog bandwidth? But I think it is a good idea anyway, because with 10 MHz it would be more accurate. |
| StillTrying:
"I guess I would need to reduce C5 then for a higher analog bandwidth?" C5's 470p seems a very large value to me, giving the op amp's output a lot to do, I'd have thought only 22 - 47p would be enough, and less chance of the output overshooting. I'd be tempted to put about 22 - 47n of decoupling on the op amps non-inverting input. |
| FrankBuss:
Right, the decoupling capacitor is a good idea after the pot. I added the same 100 nF as already used, shouldn't make a difference. And I fixed the OpAmp power supply and changed the ADC-in capacitor to 47p. Will try it in the real hardware which value makes sense. 10 MHz analog bandwidth would be nice. |
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