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6 layer PCB stack up
ali_asadzadeh:
Hi,
I'm designing a 6 layer board, I need to have these impedances, 40 Ohm for DDR3, 80 Ohm for differential signals of DDR3 and 50 Ohm single ended and 100 ohm differential for other interfaces, I'm stucked with selecting reasonably cost effective Stack up to reach my design goals,
I have calculated this stack up, with these spaces.
the problem is that,I can not make 40 ohm single ended, because the trace width would become too large(around 10mils)! so I can not route the board efectively, I need the trace to be around 4-6 mils, any Ideas what should I do?
Miyuki:
And increasing impedance ? Or you have to go to really high clock rates ?
Check signal calculation for 50 Ohm
Or even higher, all depends on distance and clock needed to keep eye diagram enough
TheUnnamedNewbie:
A single ended microstrip/stripline is always gonna give you much wider traces than a differential with two time that impedance, because you don't have all that capacitance of the nearby trace to make the thing smaller.
If you really need single-ended transmission lines, consider using something like CPW.
OwO:
DDR3 system impedance is scalable. I haven't tried this yet but you may be able to use 60ohm traces if you change the on-chip termination calibration resistors (Zq on the dram chip side and VRN/VRP on the FPGA side).
ali_asadzadeh:
--- Quote ---If you really need single-ended transmission lines, consider using something like CPW.
--- End quote ---
whats CPW?
--- Quote ---DDR3 system impedance is scalable. I haven't tried this yet but you may be able to use 60ohm traces if you change the on-chip termination calibration resistors (Zq on the dram chip side and VRN/VRP on the FPGA side).
--- End quote ---
Oh, that's good advice, and I have not tried it yet!
my DDR3 speed is 1866, so xilinx recommended 40 Ohm traces |O
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