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74 Series Logic Design: Equation optimiser?

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NivagSwerdna:
I know I am about 50 years out of date but...

Given a set of Logic Inputs and a set of boolean equations (AND, OR, NOT, XOR) is there a method to optimise for a set of 74 series ICs to realise the equations?

e.g. Given a set of equations with lots of ORs the actual best solution might be to use Quad NANDs ?

Or did designers just use pen, paper and deMorgans?

Ian.M:
If you've got a windows PC, you may find Logic Friday useful.  Its a GUI frontend for the Espresso logic minimizer  The original website's gone to domain parking, but it can still be accessed, including downloading the installer, [here] at the Internet Archive.

However that wont spot for you when it would be preferable to use MSI logic chips like a magnitude comparator, or 74xx138 and '238 three to eight line decoders, which can pick out a single condition from any four input signals, or any condition with at least one '0' input from five signals or any with two '0'and one '1' from six signals.

NivagSwerdna:
Thanks Ian.M

I couldn't get your link to work but I managed to find it here https://logic-friday.software.informer.com/download/

And it did the job instantly!

Alex Eisenhut:
Hmm, I'm also out of date but for small systems isn't that

https://en.wikipedia.org/wiki/Karnaugh_map

NivagSwerdna:
... yes and minterms and maxterms and all that.  It's nice to have some tools though!  ;)

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