Author Topic: 74HC74 Power On Reset  (Read 1394 times)

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Offline German_EETopic starter

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74HC74 Power On Reset
« on: March 23, 2019, 07:58:49 pm »
In a 74HC74 dual d-type FF do the two flip flops always power up in the 'reset' state with notQ high or do I need to make use of the two reset pins and apply a short 0 pulse on power up?

Some experiments with an NXP part and a breadboard seem to indicate some form of reset mechanism but I am not sure here.
Should you find yourself in a chronically leaking boat, energy devoted to changing vessels is likely to be more productive than energy devoted to patching leaks.

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Offline amyk

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Re: 74HC74 Power On Reset
« Reply #1 on: March 23, 2019, 08:08:57 pm »
Unless there is an explicit mention of a power-on-reset functionality, always assume that logic will power up in an undefined state.
 
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Offline Yansi

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Re: 74HC74 Power On Reset
« Reply #2 on: March 23, 2019, 08:11:10 pm »
No POR mechanism reset. use the asynchronous Set/Reset pins to init all flipflops to known states. (back in the days, chips like 7705 were used for this).
 

Offline German_EETopic starter

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Re: 74HC74 Power On Reset
« Reply #3 on: March 24, 2019, 09:35:15 am »
OK, thank you for confirming this. One trick I found years ago for a simple power on reset was to connect a 100n capacitor from the reset pin to ground, on power up it holds the reset pin low just long enough for it to be effective.
Should you find yourself in a chronically leaking boat, energy devoted to changing vessels is likely to be more productive than energy devoted to patching leaks.

Warren Buffett
 


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