"Underclocking" Ethernet transceivers (using them below standard speeds)

[KhronX]

That's as a "maybe" - as in the video linked by bktemp in the 2nd post here, such a thing COULD potentially be achieved. Micah managed to still have reliable TCP/IP comms on a 10Mbps link slowed down to... 25 / 6 = ~4, so down to about 2.5Mbps 

An ethernet PHY is much more complex inside than you may think, it's not just a transceiver. The PLL for clock recovery is designed to work at the ethernet line rate, it will not work at your bitrate. It's not as easy as changing the phy xtal or oscillator.

[technogeeky]

Most of the solutions in this thread are above my head. Heck, the question itself may be beyond me at the moment.

But couldn't you do signaling at full speed but simply insert dummy data at the TX point and strip it at RX point? I am imagining reserving for instance audio content consisting of large blocks of all ones (which I suppose would correspond to a maximum audio signal) which you would forbid from being considered a real signal. Then you just insert ~3 of these packets for every ~1 ADAT packet and strip them at the receiver stage.

Having typed this nonsense, I think it might introduce more problems; but hey, Merry Christmas.

[technix]

I wonder if you can just tunnel the audio data through normal UDP packets, using normal Ethernet infrastructure?

The STM32F107 came into my mind, as it have (R)MII and I2S support. You can program the MCU to handle the ADAT packets as-is, tunneling it through UDP/IP by slapping UDP, IP and Ethernet headers onto it. On the other hand you can use an ADAT to I2S interface to take the raw audio stream and package it into RTP/RTSP, maybe throw in some lossless encoding like FLAC or ALAC for easier computer consumption.

[KhronX]

If at all possible, i'd prefer avoiding any and all programming 

I got to thinking yesterday, that i might just have to try out my initial idea (RS485 driver chip hooked up straight to a MagJack), and see just how horrible that ten-zero-bit (encoded) synchronization frame looks on the scope, at the other end. 

[technix]

If it is the isolation you are eagering for, you can use a small FPGA or MCU to insert (or remove) a lot of EDAC code and a high overhead line code, and use the PHY at full speed.

Inserting EDAC code adds redundancy that can combat data corruption, thus you can get a longer cable run out of it. Normal Ethernet have a 100m run limit. With a lot of excessive EDAC you may get half a mile out of it.