Yes, would be much more interesting if it took advantage of the more analog properties of the device. Example: if input signals are well buffered, then summing them together with resistors gets you an analog level, which compares to the internal threshold, and there you go, a COUNT(N; a_1, a_2, ..., a_n) operator. Which, if the threshold is N=1, you get a standard (N)OR gate; or N=n, (N)AND.
Would also like to see tooling to accompany the architecture -- four measly instructions is the most boring thing I can think to assemble. Doing basic arithmetic and flow control would be nice; maybe implementing a VM with a nicer architecture, albeit even slower in operation.
Or, another interesting question might be: at the expense of adding one or a few instructions, or lengthening instructions (say to allow more memory space, or various addressing ranges, or modes even), how much nicer/easier/faster does that next level VM get?
Ultimate question, for any combination of HW/SW architecture: how long until it runs C?

(After which, Doom is only a few keystrokes away, natch.)
Tim