Electronics > Projects, Designs, and Technical Stuff
A retrocomputing project, details of the journey
slburris:
I've been working on the I/O decoding and memory decoding, and the design
was starting to take up quite a few jelly bean logic chips.
So to symplify things yet stay with technology of the era, I've decided to
sweep the glue logic into a GAL chip. Yes, I should probably use a PAL,
but I don't have any, and I don't fancy programming one-time programmable
chips anyway, since I invariably get things wrong!
In my junk box, I have a bunch of ATF22V10, which is Atmel's GAL22V10 chip.
I haven't touched anything like this in years. These days I program FPGAs
and CPLDs in VHDL. But GALs?
Time to wrap my head around WinCUPL and try to remember how you program
in this language. It sure seems much clumsier to me than VHDL....
Anyone, here's my first shot at the CUPL description for the GAL:
Name z80 ;
PartNo 00 ;
Date 9/24/2010 ;
Revision 01 ;
Designer Engineer ;
Company - ;
Assembly None ;
Location ;
Device g22v10 ;
/* input pins */
pin 1 = !reset;
pin 2 = !mreq;
pin 3 = !iorq;
pin 4 = !rd;
pin 5 = !wr;
pin 6 = !m1;
pin [7..9] = [a5..a7];
pin 10 = a15;
/* output pins */
pin 14 = !siosel;
pin 15 = !ctcsel;
pin 16 = !piosel;
pin 17 = !cfsel;
pin 18 = !memlow;
pin 19 = !memhigh;
pin 22 = !promena;
field ioaddr = [a5..7];
field iosel = [siosel,ctcsel,piosel,cfsel];
field iodecode = [sio,ctc,pio,cf,mem];
table ioaddr => iodecode {
[00..1f] => 'b'10000;
[20..3f] => 'b'01000;
[40..5f] => 'b'00100;
[60..7f] => 'b'00010;
[80..9f] => 'b'00001;
}
siosel = !m1 & iorq & sio;
ctcsel = !m1 & iorq & ctc;
piosel = !m1 & iorq & pio;
cfsel = !m1 & iorq & cf;
memena = !m1 & iorq & mem;
promena.ar = memena;
promena.sp = 'b'1;
memlow = mreq & !a15 & (!rd # !promena);
memhigh = mreq & a15 & (!rd # !promena);
slburris:
Lets try posting again, first time didn't work....
Time for an update.
I've completed 90% of the schematic work and attached the three schematic
sheets to this posting.
I've done a layout of the PCB and did a preliminary routing test.
Next up, I need to finished the schematic and PCB, print out the PCB at
actual size, get all the components together, and do a fit test on paper.
Once that all looks good, then it will be time to order PCBs and build
a prototype.
Scott
Zad:
Maybe it is because I am a hardware person rather than a software one, but give me logic gate diagrams any day, so much easier to understand what is going on!
:D
slburris:
Test to see if posting to this topic still works.
slburris:
Going to continue in "Retrocomputing, part 2"
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