Review request: Clock generation for ADC

[davegravy]

Here's the Crystal Oscillator IC I've selected for my project. I've been looking for application notes and reference designs to try and better understand how to use it and lay it out on PCB optimally. Most of what I've found relates to crystals that I think are meant to be driven by external circuitry versus this device which is more turnkey.

I'm hoping the lack of detail in the datasheet and separate whitepapers is because it's such a simple device to use.

Schematic and pcb layout is attached.

Objective is to generate 8.192MHz using the ECS oscillator (IC8), divide it by 10 using the decade counter (IC6), then resync the divided clock with the original clock from the ECS oscillator using a D flipflop (IC7). This should produce 819.2kHz MCLK which goes direct to the ADC. I'm not sure what to do with Pin 1 of the oscillator, it seems from the datasheet if I don't need a disable then leaving it floating is fine?

Do I need to worry about this circuit causing noise in my power supplies nets or anything like this?
I'd appreciate if anyone can point out any errors or better ways to do this. I would directly use a 819.2kHz oscillator instead of dividing, but these don't seem to be available right now.

[moffy]

The 74HC390: I would join pin 3 to 4 and take my output from pin 7 to the D FF.
I would also GND all unused inputs, CLK and RESET to prevent unwanted toggling. Can produce some unexpected and noisy results.
You can pull pin 1 of the oscillator high through a resistor or directly to VCC if you want or leave it floating.

[fourfathom]

The 74HC390: I would join pin 3 to 4 and take my output from pin 7 to the D FF.

Of course you would also connect the oscillator output to the HC390 pin #1.  But doing it like this will add some jitter to the div-by-10 output, since you now have two cascaded clock-Q delays.  I assume this is why the OP added that re-timing DFF.  There are fully-synchronous divide-by-10 chips out there so you might be able to eliminate the re-timing flop.

Yes, unused inputs should be terminated appropriately.

As for power supply noise, those oscillators aren't that difficult to use.  Your 0.1uF bypass is nicely placed, and there shouldn't be much noise induced into the rest of the board.

Yes, pin 1 can be floating or tied to VCC.  It looks like there's an internal pull-up on that pin.  Unless you want the option to add a jumper "bodge" wire for testing, you might as well connect it to VCC.

[davegravy]

The 74HC390: I would join pin 3 to 4 and take my output from pin 7 to the D FF.

Of course you would also connect the oscillator output to the HC390 pin #1.  But doing it like this will add some jitter to the div-by-10 output, since you now have two cascaded clock-Q delays.  I assume this is why the OP added that re-timing DFF.  There are fully-synchronous divide-by-10 chips out there so you might be able to eliminate the re-timing flop.

Thanks,

I think you two are advocating the BCD connection scheme rather than bi-quinary? I chose Bi-quinary mainly because it provides a 50% duty cycle. My  ADC is sensitive about where the clock edges fall, ie that they don't occur within the conversion phase. I know I'm ok with 50% duty cycle, it looks like the BCD method you're proposing gives 80%, or am I misunderstanding something?

[moffy]

As you stated if you want 50% duty cycle then your original connection is best, /2 after /5.