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AD7799 ADC Supply Voltages Setup When Battery Powered??........

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I'll lead off with the question:
  "If trying to get full resolution from the converters, what is the optimal power supply configuration when running the AD7799 from a single Li-Ion battery (2.5-4.2V)?"
I'm sort of surprised there is no app note about this specifically. 

Lets say I'm using this part with a bridge type load cell as shown in the typical circuit (without that NTC thermistor part), and that it will be in use for a few hours at a time.  I want to use the upper ranges of PGA gain and sample rate, which means I don't get to waste bits with supply noise:

Analog Devices AD7799
"3-Channel, Low Noise, Low Power, 24-Bit, Sigma Delta ADC with On-Chip In-Amp"
Product Page = https://www.analog.com/en/products/ad7799.html
Data Sheet = https://www.analog.com/media/en/technical-documentation/data-sheets/AD7798_7799.pdf

This part has three voltage requirements:
1) DVdd = 2.7-5.25V = Digital Supply for microcontroller IO interfacing.
2) AVdd = 2.7-5.25V = Analog Supply, and excites the load cell.
3) VREFIN = 0.1-AVdd = Reference voltage, recommended 2.5V.

Option 1: Power everything from 2.7V with LDOs right off the battery?
Use one LDO direct from the battery to make AVdd=2.7V, and another LDO for VRefin=2.5V. 
Probably use another separate LDO to make DVdd 2.7V and also power the microcontroller with that rail? 
This seems like it's the lowest noise, but wastes battery capacity (lowest the battery can be drained is 2.7V + Drop out) and it's burning power at full battery charge (4.2 - 2.7).

Option 2: Boost/Buck to make 3.3V, then down regulate from there?
Run a buck/boost regulator off the battery to make the 3.3V.  Use that 3.3V to power DVdd and the micro.
The VRefin 2.5V can still be an LDO right on the battery, but where should the AVdd come from?  LDO at 3V on the 3.3V rail?  Just filter the hell out of the 3.3V from the buck/boost and use that for AVdd?

Option 3:
Something completely different?

The reference board for the AD7799 has really bad circuit operation descriptions and all the jumpers and configuration options make the schematic a mess: https://www.analog.com/media/en/technical-documentation/evaluation-documentation/EVAL-AD7799.pdf

This is an app note for a similar chip, AD7781, that has a better circuit with power supply filtering, but it still assumes you are starting with 5V:


I would go for a single 2.7 V LDO.  Lion cells don't like operation much below 3 V. I doubt it would be worth the effort for a boost converter for the tiny bit of energy left when already below 2.8 V.  In most cases one would turn off already before that.
There is usually no need for a seprate regulator for the digital supply - just extra decoupling and maybe some filtering for both AVDD and DVDD and also the ┬ÁC.

For a brigde using the supply as reference should be OK, just like the circuit from the DS.

With relatively low power levels a SMPS is not that efficient. It can be more efficient to loose 1 V at the LDO than providing the power to the SMPS chip just to run essentially idle. Anyway 4.2 V would be on the high side and only for a short time. AFAIK most of the time the votlage is below 4 V.  On average it would be some 3.6 V for the input side and thus some 0.9 V drop.

Using avdd for the reference is an interesting thing.  All of the datasheet and app note examples do that, but they also only show a single bridge hooked up to the inputs.  This is strange considering the part has three bridge inputs.  There is a note on the datasheet that talks about using avdd as the reference as long as you only have one bridge in ratiometric mode, but if you have multiple bridges you should use a separate low noise reference. 

You also lose some range if your reference is the same voltage as the avdd.

One could still used the supply with more than one bridge. Ideally one may have to also switch the ref sense part with the bridge. An alternative would be using extra drive and sense for the bridges, but this would likely no longer be low power and may need an extra supply.
Even with just 1 lower resistance (e.g. PT100 or DMS) bridge that is connected via longer cables, there should be 6 wires to the bridge: 2 for the bridge supply, 2 for the ouput signal and another 2 to sense the actual bridge voltage. One may be able to skip seprate ref sense if the bridge is higher resistance, like 10 K NTC. A PT100 bridge may anyway need a reduced supply to the bridge (or a asymmetric bridge, like PT100 and 1 K or even 3 K in series to avoid excessive current).
For the reference bridge drive it is important to have low noise in the higher frequency range, where the ADCs modulation happens (e.g. 10 kHz - 10 MHz). The lower frequence noise is not that relevant in a ratiometric setup.

The bridge I'm planning on using is a tension/compression load cell, with resistance in the 350 Ohm range (from excitation + to -).  The cable only has 5 connections (Excitation+/-, Signal+/-, and cable shield), so no separate sense connections right at the bridge.

From this app note: https://www.analog.com/media/en/reference-design-documentation/reference-designs/CN0216.pdf
"Unlike a 6-wire load cell, a 4-wire load cell does not have sense pins, and the ADC differential reference pins are connected directly to the excitation voltage and ground. With this connection, there exists a voltage difference between the excitation pin and the reference pin on the ADC due to wire resistance. There will also be a voltage difference on the low side (ground) due to wire resistance. The system will not be completely ratiometric. "

With a 350Ohm resistance at 2.7V that's like 8mA per bridge.  The AD7799 does have that switch to ground pin that disconnects the bridges at the low side, but I would imagine that in continuous measurement mode that's always connected.

The first iteration of this design is indeed only one bridge, but the next version will need two bridges connected.  It would be excellent to have this board be able to accommodate both configurations.


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