EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: technix on May 12, 2015, 10:56:03 pm
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This is also a board layout validation. Eagle DRC found no issue.
Both sides are filled with GND, and there is a lot of GND via stitching. Components are double side loaded.
I never found the internal 3.3V "regulator" of CH340G reliable so I added an AMS1117 to help it. Power rails are done extra thick.
I always found the USB B connector extra reliable when connected through hole. So that is what I used.
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One suggestion you might want to add a pad for a small cap, so you can do the arduneo auto reset bit. Assuming you plan to sell to to others. So on dts you could put a .1uf cap in line with dts then have a cutable trace that shorts out the cap, or bridgeable.
Ex: of what you have to do on other modules currently for sale.
https://hackaday.io/page/416-serial-auto-reset-mod
Also i like to see Rx tx DTS etc on the silkscreen as well as arrows pointing direction of data flow.
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One suggestion you might want to add a pad for a small cap, so you can do the arduneo auto reset bit. Assuming you plan to sell to to others. So on dts you could put a .1uf cap in line with dts then have a cutable trace that shorts out the cap, or bridgeable.
Ex: of what you have to do on other modules currently for sale.
https://hackaday.io/page/416-serial-auto-reset-mod
Also i like to see Rx tx DTS etc on the silkscreen as well as arrows pointing direction of data flow.
Added them. The cap footprint is in the back of the board, C5.
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Why not just add some jumper pins so C5 can be in circuit or shorted out with a jumper.
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Net name D+ is missing.
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Why not just add some jumper pins so C5 can be in circuit or shorted out with a jumper.
Nope, that just makes th board too complicated.
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Net name D+ is missing.
There is no missing net.
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Net name D+ is missing.
There is no missing net.
I said name, not net.
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Net name D+ is missing.
There is no missing net.
True, but why name it N$2?
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Net name D+ is missing.
There is no missing net.
True, but why name it N$2?
Net rename misfire. Still works so not bothered to change.
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Naming the D+ net is something I would do, personally, but it makes no difference to the electrical correctness of your design. It's just something that contributes nice readability and documentation to a schematic, which is separate from electrical correctness.
Personally I'd probably specify the PPTC trip current, value or part number on the schematic, too.
Most Arduino-like devices that use an FTDI serial cable (or FTDI cable-compatible adapter board, like yours) actually have the reset coupling capacitor on the target board, and the UART adapter device provides a connection straight to logic-level CTS or RTS. So in that regard I think your original design, without modification, is "correct" in that it is compatible with the defacto standard for this kind of device - same as an FTDI cable.
I would avoid double-sided component loading if you can possibly avoid it - if you're ever aiming for "real" manufacturability at scale it adds cost.
Having named nets (eg. for DCD, RI and the other UART lines) will cause an Eagle ERC error if they're not actually used (i.e. not connected to some sort of component at at least two points.)
I would put a decoupling capacitor on the power rail as close as possible to where it enters the IC - a separate cap, in addition to the one at the LDO regulator.
That's just good practice though, in practice for a small design with one IC and the IC being close to the LDO it would probably work fine.
Using a big USB-B connector seems unusual today compared to mini-B or micro-B - it's your choice though, and there's nothing "wrong" about it.
The vias under the IC look a bit close together - try making the drills smaller, what's the drill size?
What's the CH340G like, anyway? I'd like to know how well it stacks up as a usable replacement for, say, FTDI silicon.
Does it "just work" with nice driver support on Windows, Linux and OSX?
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Naming the D+ net is something I would do, personally, but it makes no difference to the electrical correctness of your design. It's just something that contributes nice readability and documentation to a schematic, which is separate from electrical correctness.
Personally I'd probably specify the PPTC trip current, value or part number on the schematic, too.
Most Arduino-like devices that use an FTDI serial cable (or FTDI cable-compatible adapter board, like yours) actually have the reset coupling capacitor on the target board, and the UART adapter device provides a connection straight to logic-level CTS or RTS. So in that regard I think your original design, without modification, is "correct" in that it is compatible with the defacto standard for this kind of device - same as an FTDI cable.
I would avoid double-sided component loading if you can possibly avoid it - if you're ever aiming for "real" manufacturability at scale it adds cost.
Having named nets (eg. for DCD, RI and the other UART lines) will cause an Eagle ERC error if they're not actually used (i.e. not connected to some sort of component at at least two points.)
I would put a decoupling capacitor on the power rail as close as possible to where it enters the IC - a separate cap, in addition to the one at the LDO regulator.
That's just good practice though, in practice for a small design with one IC and the IC being close to the LDO it would probably work fine.
Using a big USB-B connector seems unusual today compared to mini-B or micro-B - it's your choice though, and there's nothing "wrong" about it.
The vias under the IC look a bit close together - try making the drills smaller, what's the drill size?
What's the CH340G like, anyway? I'd like to know how well it stacks up as a usable replacement for, say, FTDI silicon.
Does it "just work" with nice driver support on Windows, Linux and OSX?
I was naming that N$2 net D+ but a via renaming FU turned it into N$2. Never bothered to change it back since the circuit is still correct but I will change it back before releasing it open source, after the first board spin turned out to be okay.
I double checked the connection and this pinout matched the SparkFun FTDI pinout. The cap is shorted out on the board and not populated.
I chose USB B connector for its reliability. I once broke an Arduino Leonardo clone by snapping the USB connector off the board, ripped a few traces and damaged the board beyond repair.
My board house can handle that precision manufacturing at no extra cost so it is okay.
CH340G works fine under Windows 8, OS X Yosemite and Ubuntu 14.04 and that is what I have tested it on.
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CH340G works fine under Windows 8, OS X Yosemite and Ubuntu 14.04 and that is what I have tested it on.
Does it require driver installation?
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CH340G works fine under Windows 8, OS X Yosemite and Ubuntu 14.04 and that is what I have tested it on.
Does it require driver installation?
I cannot recall clearly. On older versions of Windows and OS X a vendor-provided driver package is required. I vaguely remember that OS X Yosemite have this driver built in, and Windows have its driver in Windows Update and can be installed online.
If you use Linux, no driver is required if your kernel is recent enough.
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Thanks. I will give it a try.
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How does the CH340G perform at bit banging, is it as good as the FTDI chip?
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How does the CH340G perform at bit banging, is it as good as the FTDI chip?
It does not have a bit bang mode.