5. Output pole is cancelled when Cout impedance turns resistive and stops falling with frequency.
4. Finite output resistance of the buffer plus parasitic capacitance being driven, I suppose. Why wouldn't it?
3. Low dynamic resistance compared to a resistor?
I'm no CMOS LDO design wizard by any stretch of imagination, but it looks like they anticipate increased loop gain due to output device transconductance rising with increased load current (but not with decreased load resistance
as that would simultaneously reduce loop gain back to square one, methinks). So they mirror fraction of load current to the buffer to up its bandwidth.
Huh, if your professor says it works, who am I to disagree