Electronics > Projects, Designs, and Technical Stuff
ADC and serial circuit improvement advice
blazini36:
--- Quote from: Kleinstein on August 18, 2019, 06:20:36 pm ---In the level translator the mosfet works like an ideal diode, possibly just from the substrate diode (depending on the sample, the mosfet may not conduct with 3.3 V gate voltage). So this can be fast going H to L, but it is slow going L to H. So just a divider can be about as fast.
--- End quote ---
I could use a divider, it's easier. What do you think about level shifting with a double inverter? Something like this http://www.ti.com/lit/ds/symlink/sn74lvc2g04.pdf
1A would be the input for the receiver output, 1Y is the inverted output to to 2A, then 2Y is the final output to the GPIO FPGA pin @ Vcc of 3.3v. Seems that is should switch in each direction at 10ns.
blazini36:
Any thoughts on this one?
Kleinstein:
The double inverter should work too. When going to an FPGA one usually does not care about the polarity - so a single inverter would be enough.
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