I'm working on a motor driver and have found an interesting (maybe?) issue with my ADC setup.
I copied the config from the open source VESC firmware which runs the F405 at 168MHz and the ADC at 42MHz which is actually out of spec - the datasheet says 36MHz max. However, this does seem to work and is used in one of the STM32 examples for that chip.
The VESC also configures the ADC for the minimum sampling time of 3 Cycles.
I suppose it's a surprise this works at all - the ADC is running above spec and sampling for a tiny amount of time.
This config works for me ONLY if I've got an external filtering capacitor attached. I've got a switchable low pass filter that uses either 220pf (off) or 220nf (on) and when "off" the voltage is wrong.
Increasing the ADC sample time to > 54 cycles or enabling my low pass filter result in the same reading which agrees with my mutli meter, scope and psu.
The odd bit, and the reason for posting, is the wrong reading is higher than the input voltage and I can't think how that could happen. The adc connects the sample and hold cap to the DC signal and if it's connecting for too short a time it reads ~20% high???
I wouldn't be surprised if the VESC hardware has similar quirks but ultimately it doesn't really matter because the absolute voltages don't really matter as long as they are self-consistent and more or less linear.
So, the question is, how can an ADC read higher than the highest DC in the system when the sampling period is too short?
I've attached the schematic for the switchable low pass filter for clarity.