Author Topic: Adjust data relative to clock  (Read 3825 times)

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Offline ataradovTopic starter

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Adjust data relative to clock
« on: January 15, 2020, 11:13:08 pm »
I'm looking for ideas for a vague project, so things are not well defined.

Basically I have a parallel bus that has 1-8 data signals and one clock signal. The frequency of the clock signal is 10-100 MHz. The data is going to be received by the FPGA.

The problem is that due to routing and wiring, the signals may be slightly misaligned, between themselves and the clock.

The goal is to have a way to slightly shift the clock by a few ns in a few steps. For now let's assume that the signals are aligned, but the clock is shifted, since shifting the clock may provide a way to find a common sampling point between the signals.

Additional issue is that it may be a DDR clock, so the data is sampled on both the rising and falling edges. So whatever method is used, it must preserve the duty cycle.

But one thing that may help is that clock is constantly running, so the actual delay may be a few ms + a few ns. It will make no difference to the end result.

And the accuracy of the delay and its variability from device to device or even from power cycle to power cycle does not matter. The correct delay will be calibrated every time to get reliable reception of a known test pattern.

I know some FPGAs have capabilities to shift the clock, but for now I would like to plan on using the external circuitry so that my choice of FPGAs is not limited by this factor.

I have some ideas of forcing a chain of inverts inside the FPGA, but I have never tried anything like this, so I don't know if this will be close to working.

Any ideas for external circuitry are welcome. Complexity and price are factors. So $20 delay lines are out of the question.
Alex
 

Offline unitedatoms

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Re: Adjust data relative to clock
« Reply #1 on: January 15, 2020, 11:37:21 pm »
There are digital clock fanning chips with 5 bit resolution for absolute delay or more. Ad9513. Unless that what you meant by $20 delay line.
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Offline ataradovTopic starter

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Re: Adjust data relative to clock
« Reply #2 on: January 15, 2020, 11:40:35 pm »
There are digital clock fanning chips with 5 bit resolution for absolute delay or more. Ad9513. Unless that what you meant by $20 delay line.
Yes, that's exactly what I mean. AD9513 is $8.6 in 500 qty.

The solution I'm looking for is something in the realm of varicap and buffered RC delay. I'm looking for something under $1, basically no matter how dodgy it may appear, as long as it works.
Alex
 

Offline unitedatoms

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Re: Adjust data relative to clock
« Reply #3 on: January 15, 2020, 11:50:38 pm »
For 2 bit resolution there is polyphase filter
Looks like just a gate with single input, two complimentary outputs, L C and 4 Schmitt gates can work as digital equivalent.

https://wiki.analog.com/university/courses/electronics/comms-lab-polyphase-filter
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Offline james_s

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Re: Adjust data relative to clock
« Reply #4 on: January 16, 2020, 12:41:32 am »
Seems like doing this sort of thing in an fpga typically involves using a faster internal clock in the FPGA, then you can use that to drive a counter or flip flop that samples the incoming clock and applies a slight delay.
 

Offline ataradovTopic starter

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Re: Adjust data relative to clock
« Reply #5 on: January 16, 2020, 12:45:47 am »
Nobody over-samples 100 MHz clock. That is not going to work reliably at all. Or you will need a way more expensive FPGA, and even then it is still questionable.
Alex
 

Online David Hess

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Re: Adjust data relative to clock
« Reply #6 on: January 19, 2020, 07:59:29 pm »
The solution I'm looking for is something in the realm of varicap and buffered RC delay. I'm looking for something under $1, basically no matter how dodgy it may appear, as long as it works.

That can work but to get negative delay, the delay has to start at 1 or a whole number of cycles.

A common way is to phase lock an oscillator to the clock signal and then adjust the phase by adding an offset to the output of the phase comparator.
 

Offline ataradovTopic starter

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Re: Adjust data relative to clock
« Reply #7 on: January 19, 2020, 08:10:55 pm »
That can work but to get negative delay, the delay has to start at 1 or a whole number of cycles.
Negative delay is not a problem. There is no correspondence of the specific clock cycle to the data. The clock is continuous and if there is no data to be sent, data lines are just stuffed with dummy data. So to get negative delay we just need to overflow into the next cycle.

A common way is to phase lock an oscillator to the clock signal and then adjust the phase by adding an offset to the output of the phase comparator.
One thing that gives me pause with generating secondary clocks is that data is sampled on both edges. I do expect duty cycle of the original clock to be close to 50%, but who knows, especially at high frequency. Secondary oscillator will definitely "fix" the duty cycle.
Alex
 

Offline Yansi

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Re: Adjust data relative to clock
« Reply #8 on: January 19, 2020, 09:03:19 pm »
Nobody over-samples 100 MHz clock. That is not going to work reliably at all. Or you will need a way more expensive FPGA, and even then it is still questionable.

mind your language... Here they've been oversampling even 420Mbps serial streams x4.

https://www.xilinx.com/support/documentation/application_notes/xapp224.pdf

Yet it was I guess working pretty well.

Note: Varactor controller RC delay is crap, forget it. Way too much jitter. Better solution would be to start from scratch and fix the problem (clock misalignment) in the first place, instead of trying to come around it.
« Last Edit: January 19, 2020, 09:05:15 pm by Yansi »
 

Offline Benta

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Online David Hess

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Re: Adjust data relative to clock
« Reply #10 on: January 20, 2020, 04:53:15 am »
A common way is to phase lock an oscillator to the clock signal and then adjust the phase by adding an offset to the output of the phase comparator.

One thing that gives me pause with generating secondary clocks is that data is sampled on both edges. I do expect duty cycle of the original clock to be close to 50%, but who knows, especially at high frequency. Secondary oscillator will definitely "fix" the duty cycle.

It is not difficult to add another analog control loop which measures the input duty cycle and adjusts the output duty cycle to match.  Usually this is done to make a precision variable duty cycle.
 

Offline OwO

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Re: Adjust data relative to clock
« Reply #11 on: January 20, 2020, 06:12:49 am »
PCB delay lines + $0.1 RF switches (mxd8641 etc) might do the job. 4 sp4t switches and some PCB traces can implement 16 delay steps. Ignore the frequency ratings in the datasheet; these switches can all operate down to DC for low voltage signals, but check whether 3.3V can pass without getting clamped.
« Last Edit: January 20, 2020, 06:14:44 am by OwO »
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Online langwadt

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Re: Adjust data relative to clock
« Reply #12 on: January 20, 2020, 08:40:00 pm »
PCB delay lines + $0.1 RF switches (mxd8641 etc) might do the job. 4 sp4t switches and some PCB traces can implement 16 delay steps. Ignore the frequency ratings in the datasheet; these switches can all operate down to DC for low voltage signals, but check whether 3.3V can pass without getting clamped.

sure but it'll need a very long delay line, because once you add stuff and a clock buffer you are already behind and need atleast half a cycle delay to catch up (assuming 50/50 duty)
 

Offline ogden

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Re: Adjust data relative to clock
« Reply #13 on: January 20, 2020, 08:52:54 pm »
I know some FPGAs have capabilities to shift the clock, but for now I would like to plan on using the external circuitry so that my choice of FPGAs is not limited by this factor.
Whole idea of doing clock skew management outside FPGA is wrong. After all (both) leading FPGA camps offer proven solutions, just copy/paste them.
 

Offline edavid

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Re: Adjust data relative to clock
« Reply #14 on: January 20, 2020, 09:04:46 pm »
PCB delay lines + $0.1 RF switches (mxd8641 etc) might do the job. 4 sp4t switches and some PCB traces can implement 16 delay steps. Ignore the frequency ratings in the datasheet; these switches can all operate down to DC for low voltage signals, but check whether 3.3V can pass without getting clamped.

Since it's a digital delay, there's no need to use analog switches.  He could use a digital mux or just extra FPGA inputs.  A gate chain can be used to get more delay in a smaller space.

For high resolution tweaking, use a gate chain, but adjust the supply voltage to vary the delay.  (This may also need level shifters.)
« Last Edit: January 20, 2020, 09:06:53 pm by edavid »
 

Offline Yansi

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Re: Adjust data relative to clock
« Reply #15 on: January 20, 2020, 09:14:37 pm »
A gate chain can be used to get more delay in a smaller space.

For high resolution tweaking, use a gate chain, but adjust the supply voltage to vary the delay.  (This may also need level shifters.)

can be used to get delay and also jitter as a bonus, can't it?
 

Offline ataradovTopic starter

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Re: Adjust data relative to clock
« Reply #16 on: January 20, 2020, 09:16:16 pm »
At this point I will have to just try a few things and see what works and what does not.
Alex
 

Offline ogden

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Re: Adjust data relative to clock
« Reply #17 on: January 21, 2020, 03:57:09 am »
At this point I will have to just try a few things and see what works and what does not.
Yes indeed, yet you have to do better than "just try". You need to properly characterize your solution in whole temperature and component tolerance ranges - to avoid picking edge solution which may possibly fail when you least expect it.
 

Offline ataradovTopic starter

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Re: Adjust data relative to clock
« Reply #18 on: January 21, 2020, 04:03:45 am »
Temperature is not as much of a factor, this stuff is going to be operated by humans. I don't care if it fails at -40 C or +85 C. Operators will fail much faster.

I also don't care as much for slow drifts. As long as things stay more or less stable for a few minutes to a few hours at a time, I'm fine.

As long as I get a few distinct sampling points from different settings, it should work.
Alex
 

Offline OwO

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Re: Adjust data relative to clock
« Reply #19 on: January 21, 2020, 04:14:49 am »
I would say analog switches (or better, RF switches) are preferred because they introduce the least jitter as the signal path is passive. The RF switches I mentioned have very low insertion loss at these frequencies, so no clock buffering is needed (assuming the delay lines are not too lossy).

Length of delay lines will be the biggest problem, especially at lower frequencies and if you want to roll over into the next cycle. You need around 16cm for 1ns of delay. If this is a 4 layer board you can have very thin 50ohm traces, but also consider using a non-50ohm Z0. The dominant loss contributor of the RF switches at low frequencies is the series resistance (the shunt capacitance is 100-200 femtofarads and can be ignored), so using a high Z0 will also reduce loss. On a 2 layer board (1.0mm thick) I would use 0.2mm traces which are 120ohm.
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Online KE5FX

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Re: Adjust data relative to clock
« Reply #20 on: January 21, 2020, 04:23:43 am »
What's wrong with an IDELAY element?
 

Offline ogden

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Re: Adjust data relative to clock
« Reply #21 on: January 21, 2020, 04:26:13 am »
Temperature is not as much of a factor, this stuff is going to be operated by humans. I don't care if it fails at -40 C or +85 C. Operators will fail much faster.
Sometimes just 30 degrees (10..40oC) is enough to bust overconfident engineers.

What's wrong with an IDELAY element?
There's no excitement of invention :-DD
« Last Edit: January 25, 2020, 07:54:42 pm by ogden »
 

Offline ataradovTopic starter

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Re: Adjust data relative to clock
« Reply #22 on: January 21, 2020, 04:28:11 am »
What's wrong with an IDELAY element?
Absence of such thing in Lattice LCMXO2, which is currently a target FPGA.
Alex
 

Offline ogden

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Re: Adjust data relative to clock
« Reply #23 on: January 21, 2020, 04:31:47 am »
Absence of such thing in Lattice LCMXO2, which is currently a target FPGA.
Oh... Is it so that Lattice do not offer *any* kind of I/O delay management?
[edit] Seems like they do, (Technical Note TN1131, apr 2007) just LC series is not in the list of said tech note.
« Last Edit: January 21, 2020, 04:35:04 am by ogden »
 

Offline ataradovTopic starter

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Re: Adjust data relative to clock
« Reply #24 on: January 21, 2020, 04:34:06 am »
Oh... Is it so that Lattice do not offer *any* kind of I/O delay management?
I have not looked in the details. 

Again, I know the answer "just use dedicated resources". There is no need to repeat it.

I was specifically looking for alternative solutions.
Alex
 


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