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Adjust data relative to clock

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David Hess:

--- Quote from: ataradov on January 19, 2020, 08:10:55 pm ---
--- Quote from: David Hess on January 19, 2020, 07:59:29 pm ---A common way is to phase lock an oscillator to the clock signal and then adjust the phase by adding an offset to the output of the phase comparator.
--- End quote ---

One thing that gives me pause with generating secondary clocks is that data is sampled on both edges. I do expect duty cycle of the original clock to be close to 50%, but who knows, especially at high frequency. Secondary oscillator will definitely "fix" the duty cycle.
--- End quote ---

It is not difficult to add another analog control loop which measures the input duty cycle and adjusts the output duty cycle to match.  Usually this is done to make a precision variable duty cycle.

OwO:
PCB delay lines + $0.1 RF switches (mxd8641 etc) might do the job. 4 sp4t switches and some PCB traces can implement 16 delay steps. Ignore the frequency ratings in the datasheet; these switches can all operate down to DC for low voltage signals, but check whether 3.3V can pass without getting clamped.

langwadt:

--- Quote from: OwO on January 20, 2020, 06:12:49 am ---PCB delay lines + $0.1 RF switches (mxd8641 etc) might do the job. 4 sp4t switches and some PCB traces can implement 16 delay steps. Ignore the frequency ratings in the datasheet; these switches can all operate down to DC for low voltage signals, but check whether 3.3V can pass without getting clamped.

--- End quote ---

sure but it'll need a very long delay line, because once you add stuff and a clock buffer you are already behind and need atleast half a cycle delay to catch up (assuming 50/50 duty)

ogden:

--- Quote from: ataradov on January 15, 2020, 11:13:08 pm ---I know some FPGAs have capabilities to shift the clock, but for now I would like to plan on using the external circuitry so that my choice of FPGAs is not limited by this factor.

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Whole idea of doing clock skew management outside FPGA is wrong. After all (both) leading FPGA camps offer proven solutions, just copy/paste them.

edavid:

--- Quote from: OwO on January 20, 2020, 06:12:49 am ---PCB delay lines + $0.1 RF switches (mxd8641 etc) might do the job. 4 sp4t switches and some PCB traces can implement 16 delay steps. Ignore the frequency ratings in the datasheet; these switches can all operate down to DC for low voltage signals, but check whether 3.3V can pass without getting clamped.

--- End quote ---

Since it's a digital delay, there's no need to use analog switches.  He could use a digital mux or just extra FPGA inputs.  A gate chain can be used to get more delay in a smaller space.

For high resolution tweaking, use a gate chain, but adjust the supply voltage to vary the delay.  (This may also need level shifters.)

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