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Adjust data relative to clock
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KE5FX:
What's wrong with an IDELAY element?
ogden:

--- Quote from: ataradov on January 21, 2020, 04:03:45 am ---Temperature is not as much of a factor, this stuff is going to be operated by humans. I don't care if it fails at -40 C or +85 C. Operators will fail much faster.

--- End quote ---
Sometimes just 30 degrees (10..40oC) is enough to bust overconfident engineers.


--- Quote from: KE5FX on January 21, 2020, 04:23:43 am ---What's wrong with an IDELAY element?

--- End quote ---
There's no excitement of invention :-DD
ataradov:

--- Quote from: KE5FX on January 21, 2020, 04:23:43 am ---What's wrong with an IDELAY element?

--- End quote ---
Absence of such thing in Lattice LCMXO2, which is currently a target FPGA.
ogden:

--- Quote from: ataradov on January 21, 2020, 04:28:11 am ---Absence of such thing in Lattice LCMXO2, which is currently a target FPGA.

--- End quote ---
Oh... Is it so that Lattice do not offer *any* kind of I/O delay management?
[edit] Seems like they do, (Technical Note TN1131, apr 2007) just LC series is not in the list of said tech note.
ataradov:

--- Quote from: ogden on January 21, 2020, 04:31:47 am ---Oh... Is it so that Lattice do not offer *any* kind of I/O delay management?

--- End quote ---
I have not looked in the details. 

Again, I know the answer "just use dedicated resources". There is no need to repeat it.

I was specifically looking for alternative solutions.
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