Electronics > Projects, Designs, and Technical Stuff
Adjust data relative to clock
ogden:
--- Quote from: ataradov on January 21, 2020, 04:34:06 am ---Again, I know the answer "just use dedicated resources". There is no need to repeat it.
--- End quote ---
LOL. Dont' you think that sometimes reason why you receive answer you already know is... lack of *working* alternative solutions?
ataradov:
I've got all the answers I needed.
BrianHG:
--- Quote from: ataradov on January 15, 2020, 11:13:08 pm ---I'm looking for ideas for a vague project, so things are not well defined.
Basically I have a parallel bus that has 1-8 data signals and one clock signal. The frequency of the clock signal is 10-100 MHz. The data is going to be received by the FPGA.
The problem is that due to routing and wiring, the signals may be slightly misaligned, between themselves and the clock.
--- End quote ---
Some potential all inside FPGA software only alternate ideas:
If you said that the source data clock is coming at 1 frequency, or, it may be within a narrower range like 75 to 100 MHz, then is would be easy for the cheapest FPGA to sample either 8 or 16 sub phases and you may use logic to determine which phases see the correct data pattern and select the optimum center tuned phase which has no errors. This would most likely eat up 2 PLLs.
However, expecting the PLL to self tune and lock between 10 and 100MHz isn't possible unless you program a frequency counter and dynamically configure the PLLs to track the source clock. However, if that source clock freely flies all around, you will not keep up.
If your FPGA is specifying that external clock's frequency, IE tuning a sampler, or it can receive an input setting a 'band', ie 10-20Mhz, 20-40Mhz, 40-70Mhz, 70-100MHz, this makes setting up the FPGA PLL easier.
Doing this right means understanding the FPGA fabric input cells and knowledge of the PLL's capabilities in using multiple output phases and for each input pin, setting 8 fast input register and clocking each on positive and negative cycles of the 4 source PLL phases giving you 8 parallel streams sampled at 8 parallel points along the source clock. You will need to run 8 copies of you test pattern recognition software to select which stream bits aren't corrupt.
With this, you will most likely loose the duty cycle of you source clock input, but, you get an auto select-able different clock phase for each input bit.
The other method, this one samples all data bits in parallel, is just dynamically tune the FPGAs PLL output phase relative to the source clock and determine the best latching time. With this method, and 2 plls, you may lock one on the rising edge and the other on the falling edge giving you a programmable duty cycle locking points. This also means only having 1 or 2 sample streams to analyze instead of 8 in my first example which would allow single individual bit sampling.
jmelson:
--- Quote from: ataradov on January 15, 2020, 11:13:08 pm ---
The problem is that due to routing and wiring, the signals may be slightly misaligned, between themselves and the clock.
The goal is to have a way to slightly shift the clock by a few ns in a few steps. For now let's assume that the signals are aligned, but the clock is shifted, since shifting the clock may provide a way to find a common sampling point between the signals.
--- End quote ---
Even Xilinx Spartan 3 had IO functions that can shift the I/O clock on a per-pin basis. I don't know how far you can shift it, but I think a few ns is possible.
Just dig into the datasheet for the details.
Jon
Navigation
[0] Message Index
[*] Previous page
Go to full version