I'm looking for ideas for a vague project, so things are not well defined.
Basically I have a parallel bus that has 1-8 data signals and one clock signal. The frequency of the clock signal is 10-100 MHz. The data is going to be received by the FPGA.
The problem is that due to routing and wiring, the signals may be slightly misaligned, between themselves and the clock.
The goal is to have a way to slightly shift the clock by a few ns in a few steps. For now let's assume that the signals are aligned, but the clock is shifted, since shifting the clock may provide a way to find a common sampling point between the signals.
Additional issue is that it may be a DDR clock, so the data is sampled on both the rising and falling edges. So whatever method is used, it must preserve the duty cycle.
But one thing that may help is that clock is constantly running, so the actual delay may be a few ms + a few ns. It will make no difference to the end result.
And the accuracy of the delay and its variability from device to device or even from power cycle to power cycle does not matter. The correct delay will be calibrated every time to get reliable reception of a known test pattern.
I know some FPGAs have capabilities to shift the clock, but for now I would like to plan on using the external circuitry so that my choice of FPGAs is not limited by this factor.
I have some ideas of forcing a chain of inverts inside the FPGA, but I have never tried anything like this, so I don't know if this will be close to working.
Any ideas for external circuitry are welcome. Complexity and price are factors. So $20 delay lines are out of the question.