The datasheet for this one suggests that the undervoltage lockout only applies to VCC:
[attachimg=1]
so high-side current limiting on the "VM" input should work, yeah?
Ah, I missed that it has a separate Vm input, if that is truly able to operate all the way down to 0V then it should be fine, although I'd be skeptical of that without reading the rest of the datasheet.
That's what I was getting at with the comparator --- it wouldn't be driving one of the h-bridge inputs, but rather a high-side transistor controlling the flow of current into VM.
That said, I'm not sure about the particulars of a comparator vs. opamp and (MOS)FET vs. BJT in this application, and whether the shunt resistor should be on the high or low side of the entire h-bridge.
A comparator is going to be better suited to chopping the power to the inductor, an op amp is better suited to linear regulation. It looks like directly chopping the power supply to the load inductor isn't a viable option because of the low inductance, so if you wanted to do this with minimal parts and the easiest circuitry at the expense of efficiency, a linear solution with op-amp and transistor would probably be the way to go.
Conceptually, there's not really a difference between low- and high-side current regulation, it's exactly the same topology just flipped upside down. In practice, low side is usually easier because it allows your control signal (and optional readback signals) to be ground referenced, it's very easy to combine arbitrary load supply and control signal voltage levels, and you get more options in N-channel (low-side) FETs than in P-channel (high-side). The downside to low-side is that your load is NOT ground referenced. You can compromise a bit by doing low-side sensing and high-side drive, if the sense resistor is small enough then the load might be close enough to ground referenced for some applications. FET vs BJT probably doesn't make a functional difference here, since the power is pretty low.
Since you want to have this H-bridge between the constant current driver and the load, you'll need to go high side on the drive at least, because the bridge still needs to receive ground-referenced logic signals. If your sense resistor can be a low enough value it may still be fine to keep that on the low side of the bridge.
I'm assuming that the amp will get driven into saturation during h-bridge dead-time / shutdown, but as long as it doesn't lock up there I'm hoping that won't be a problem.
A comparator will be fine with this, some op-amps take a bit of extra time to come out of saturation and you might need to be concerned about that depending on what your application can tolerate. There are also some op amps with very limited differential input voltage ratings, so you'd need to make sure you don't accidentally pick one of those.
With a linear constant current driver you generally do NOT want to EVER connect the load while the driver is active. If the driver is set to deliver any amount of current while the load is disconnected, it will drive the transistor wide open attempting to get any current to flow at all, and connecting the load in that condition could give it a pretty big wallop before the loop recovers. This can be avoided with additional circuitry to detect the voltage at the load terminal and disable the driver, although this might not really matter in your application. At any rate, if you have the current setpoint and the bridge under MCU control, you can just make sure that you set the current to zero before switching the bridge around and avoid the whole problem.
Assuming MCU control, I think I would be inclined to do something like the attached. The two half-bridges shown here could be two halves of the existing bridge IC you have, the one on the right is used strictly to set the polarity, the one on the left is driven by PWM and forms a buck converter along with L
Buck and C
Buck. The frequency of the buck stage doesn't really matter as long as the L and C values are chosen to suit, but higher frequency + lower L&C means faster loop response, but that only matters to the extent that your ADC can measure the load current fast enough. Depending on the resolution and response time you need and the MCU you're using, you might want to run the PWM at a relatively low resolution and dither it so that you can run at a higher frequency. Load current is measured as (V
S1-V
S2)/R
Sense and fed back into the loop driving the PWM in software. Lots of MCUs these days have differential ADCs that could do that subtraction for you, but V
S2 can probably be assumed to change slowly enough that could measure it less frequently and subtract it in the software loop. Or you could skip measuring V
S2 entirely if you decide that the resistance of the bridge and any fluctuations in Vcc are negligible for your purposes.