adjustable 500mA bipolar current control for PCB trace electromagnet

[Zero999]

Turns out Micro-Cap is pretty cool. I managed to cook up a simulation of ajb's buck bridge idea.

I modeled the h-bridge IC using an IRF9540 and IRF540 (picked arbitrarily from the extensive catalog in Micro-Cap) and am driving with a 250kHz PWM signal as per the IC's recommended max.

PWM will be driven by a 16-bit counter on an STM32 running at 84 MHz.
Maybe timers are limited to 42 MHz?
Can't recall, but either way I'll have sufficient resolution for the PWM duty cycle for a 250kHz signal.

The chart shows multiple PWM duty cycles with the current (red) and corresponding 12-bit ADC reading to be expected.
With the 3 Ohm sense resistor I'm only using about half of the ADC's dynamic range, but I'd rather lose small-current resolution in favor of making sure I can get up to the 500mA max current in the event that the PCB traces get manufactured with a few extra Ohm of resistance.

I chose the 4.7uF and 100uH values arbitrarily.
Aside from making sure the SMD inductor can handle 500mA of current, anything else I should take a look at here when selecting components?

The inductor should be before the capacitors, not after. As drawn, the capacitors will discharge high current spikes into the MOSFETs, resulting in high power dissipation.

Driving MOSFETs like that is a bad idea, due to cross-conduction, although you'll probably get away with it, as the supply voltage is below the sum of the threshold voltages. Yes, I know it's just for the purposes of the simulation, but I thought I'd point it out anyway.

[T3sl4co1l]

I'm rather more concerned with how it was supposed to work at all... at first I thought they were wired as complementary source follower, which sucks because of the high drive voltage required (and V2 isn't labeled so who the heck knows what's going into it here), but come to think of it the P and N are on top and bottom so depending on which way the P is oriented (the symbol is conveniently missing the substrate connection so it's impossible to tell D/S apart), it's either a PMOS working into a diode, or two whole-ass diodes in series shorting out the supply.

To be clear: the simulator doesn't make any assumptions, or efforts towards realism (besides certain gimmicks in rare cases), the model is entirely up to you.  An ideal voltage source will not click off when you short it, nor will components emit magic smoke when you overpower them.  You must check yourself, whether currents are realistic, power dissipation is within limits, etc.

What you should have, is a CMOS inverter: N source to GND, P source to +V, gates tied, drains tied.  With the transistors and supply voltage shown, this won't be too bad, but will need somewhat higher drive voltage (say +8/-3V) to perform properly.

The caution about shoot-through occurs when the gate voltages are intermediate.  For these transistors, it won't be much, because they are barely on at 2-3V, but, doing this with representative types that you'd use in new design, you'll most likely have logic-level types that are barely on at merely 1V, and strongly conducting by 2-3V.  So over the 1-4V range of gate voltage, you have a problem.  As the gate voltage swings through that range, in the whatever 10s of nanoseconds it takes, huge supply currents will be drawn (maybe 10A+, depends on type and etc.).

And yeah the capacitors are just wrong.  You probably get a simulation result because the transistors are never fully switching as such, just slightly charging/discharging the capacitors -- at great expense to power dissipation.

The preferred way is to use the inductor as its own filter, or if that's not possible (again, because of the short L/R time constant), then it can be pre-filtered with an LC stage, and then the LR load connected.

(There is, by the way, a way to use transistors to directly drive capacitors, at high efficiency; but it requires inductors in the supply side instead, and is generally harder to build and operate.  I wouldn't recommend.)

Tim

[lynaghk]

Everything y'all said about the MOSFETs makes sense: adjacent caps will source current during switching (=> power losses), shoot-through possible, and Micro-Cap's symbol is frustratingly ambiguous about source/drain distinction.

Unfortunately Micro-Cap doesn't ship with a tuned SPICE model of my cheapo H-bridge driver IC, so what's the alternative?
Maybe I should just use an ideal voltage source of my PWM input signal (see attached); after all, the goal of the simulation is to help me choose values of C and L for my application to work.
The IC promises 1us switching times, so perhaps as long as my current flow settles in ~500us in the simulation, I can ignore the 1us-level timing details?

From this perspective, using 1uF caps with a 100u inductor looks like the right ballpark.

[T3sl4co1l]

1. The switching waveform isn't particularly important to the simulation.  If you're just plotting Vout(time), then the bridge is just a modulator with some gain, and the HF ripple it also generates is mostly irrelevant, or easily modeled based on a squarish wave.

So, use a PULSE source with some modest edge rate -- apparently around 0.5us.

Or don't bother at all and just look at the step response of the filter.

The key insight is that, if you're largely looking at the transient response of the filter, then ripple and its response are simply a matter of superposition: the system is linear and we can simply look at the step response plus the ripple response (if we care at all, say because the output ripple voltage is small enough to ignore).

2. Model it as some reasonable approximation.  Like a pair of transistors.  But now you need a drive circuit too, likely with some staggered timing to avoid shoot-through.  There may be slew rate control as well, hence why the output rise/fall time is so long.  Or maybe they lie about the rise time and it's actually a lot faster or slower.  And, it will generally depend on load current as well, so who knows what effect that has.

This is reasonable if you need to know the dynamics of the switching event (commutation) itself.  This concerns the inductance of the supply (the loop from +V to half bridge to GND), device capacitance, and any little things you have hanging off the output (usually something like R+C or diode snubbers, if any -- which is not unlike what you had before, just MUCH smaller values!).  And for this, just a few hundred nanoseconds of simulated time might suffice, modeling the output filter inductor as a constant current sink, because its current will change little during such a short time frame, meanwhile the load current at the moment of switching may be all over the place, it depends on PWM over long time scales -- it's just an initial condition at these up-close scales.

The time constants are diagnostic.  For the switching loop, you have the 100s pF of device capacitance, 10s nH of loop inductance (and ~uF of supply bypass closing the loop, which just acts like a short circuit for such time scales -- can use the AC equivalent circuit), and whatever things of similar value are attached (i.e., snubbers on the order of 100s pF, and R ~ sqrt(10nH/100pF), would be expected).  In contrast, the filter has much longer, 10s or 100s of us time constants (10s uH + ~uF), again, essentially stationary to the switching event, and conversely the switching events are essentially irrelevant to the filter response.

Tim

[artag]

You might be interested in this guy's work :

[lynaghk]

Just to follow up, I had a PCB made and was able to successfully use it as a linear motor to drive around 1mm disk magnets (see attached photo).

Background research / theory and initial measurement notes: https://kevinlynagh.com/pcb-stepper/

One interesting finding is that trying to switch the H-bridges anywhere close to 250 kHz greatly limits the current output.
Presumably the switching losses that I neglected to model in Micro-Cap are not, in reality, negligible. =D