Electronics > Projects, Designs, and Technical Stuff
[solved, I think] Altium, Differential Signals, Harnesses and Net Labeling
aandrew:
--- Quote from: jbb on August 28, 2018, 06:37:59 am ---
--- Quote from: aandrew on August 28, 2018, 02:07:19 am ---...Now if I can figure out a way to rename a bunch of nets without calling each individual one out in a net tie... this would be ideal.
--- End quote ---
Find and replace :-)
--- End quote ---
No, I don't mean like that.
The bus entries MUST be named CLKI_P[0..4], for example (with the index at the very end), but on the digitizer page, I'd like to have then named CLKI0_P/N, CLKI1_P/N (e.g. the index inside the name, not at the end).
I'm not sure how/if I can do that.
I can create a harness with CLKI_P[0..4], but I can't "join" that harness to another harness that has those five signals in a bus broken out to five individual signals: CLKI_P0, CLKI_P1, CLKI_P2, CLKI_P3, CLKI_P4. If I could do that (with a monster harness) then I could just wire up each individual signal and name it accordingly within the digitizer sheet.
I can't create a bus named CLKI[0..4]_P because the array specification must be at the very end of the signal name.
I could break out the bus to individual wires, use net ties to another set of wires with the names how I want them, but... ick.
It's hard to imagine that Altium doesn't have a way to do this.
aandrew:
--- Quote from: T3sl4co1l on August 28, 2018, 11:26:42 am ---Also, something about REPEAT not working at zero, you have to start at 1 for some reason?
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I am definitely not having any trouble with the repeat starting at zero, perhaps this is an old bug?
T3sl4co1l:
Interesting, they must've fixed that finally.
Tim
aandrew:
So I think I got it.
I placed each diffpair into a diffpair harness, then brought those harnesses into a larger one. I could then bring that harness over to an intermediate schematic sheet which just broke things out so that I could then get the individual _P and _N signals into buses which allowed me to bring them into a REPEAT(..)ed schematic sheet.
Toplevel:
Interconnect/intermediate sheet (no parts, just signal breakout and recombination):
And finally, the connection to the FPGA:
Thank you everyone for your suggestions and your help. I find it interesting that the Altium 18 docs say that index 0 is not supported, yet I'm not having any issues with Altium 17.1.
Lautaro:
in Altium 19 I just short the nets , the outputs of the repeat with the diff pairs. The compiler didnt complain.
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