I'm at my wit's end trying to figure out how to *efficiently* route differential signals from different schematic sheets.
Overview:
I have an FPGA connected to five digitizers. Each digitizer has a clock in, clock out, data bit out, start and end signals. Each of these signals is a differential pair. I've put the digitizer subcircuit on its own schematic page, and have the toplevel schematic sheet with a single digitizer sheet with REPEAT(DIG,0,4) representing the five copies of this circuit. The sheet entries for those signals are straightforward enough: each is named and placed in a REPEAT() command, e.g. REPEAT(CLKIN_P), REPEAT(CLKOUT_P).
These sheet entries are then brought out to wires with net labels, and those wires are gathered into buses and fed into a harness. The other end of the harness breaks them out into buses and those buses (not individual nets) are fed into the FPGA sheet.
Problem #1 is that the digitizer-side of the harness has six harness entries, one for each PAIR (not individual signal): e.g. one entry is "CLKO_P[0..4], CLKO_N[0..4]", another is "CLKI_P[0..4], CLKI_N[0..4]" etc., etc., but on the FPGA side, I'm trying to break that out to make use of sheet entry buses, so one harness entry on that side is "CLKO_P[0..4]" and "CLKO_N[0..4]". Altium complains of this, and I can get around it by breaking the digitizer-side harness entries into 12 instead of 6.
Problem #2 is the naming of the nets. Altium wants to see FOO_P and FOO_N for differential pairs, but you can't use repeating entries and get those. You get FOO_P0, FOO_P1 etc. I don't see a way to name them that way using [#..#] and I really don't want to use net ties to rename the nets. Altium's not a hobbyist tool; I must just not know the correct way to do this, but the online documentation from Altium is garbage when it comes to anything beyond the simple stuff.
Pictures always help:
The toplevel schematic page, showing me trying to connect 5 digitizer sheets to an FPGA sheet through a harness. I know I'm naming the buses wrong on the FPGA sheet entry, I'm trying to make Altium name things differently but it's not working:

The digitizer schematic page, repeated 5 times in the toplevel:

And the FPGA page, where I'm trying to rename the nets from the bus format FOO_P[0..4] to something which makes more sense here, which would be FOO_P0, FOO_N0, FOO_P1, etc.:

I've clearly got myself painted into a corner here. Can anyone help me untangle myself?