Interface abuse - directly connecting high speed ADC to STM32F4 or similar

[daqq]

Hi guys,

Is there any way I could use one of the interfaces on the STM32F4 or similar to directly couple a high speed ADC? The target ADC speed is around 100 MSps @ 14 or 16 bits.

The idea is, that upon a trigger event (external pulse) the DMA would just transfer a predetermined amount of samples from the ADC, clocked by the ADC clock output. No math or anything fancy involved. Once that would be done, it would inform the processor and it would work with the sample present in the memory doing whatever needs to be done.

I was wondering whether you knew of a way that could work for this?

I've been looking at the GPIOs, they have a maximal speed of 108MHz, perhaps setting the DMA to look at the input register on an event clocked from the ADC?

Thanks,

David

[mathias]

Hi daqq,

From the top of my head, the STM32 has an "external memory" interface which should be able to use DMA.  This interface goes by the name "FSMC".

Take into account that the STM32 only has CMOS inputs, no LVDS/CML/ECL/...

Cheers!

[Psi]

I've been looking at the GPIOs, they have a maximal speed of 108MHz, perhaps setting the DMA to look at the input register on an event clocked from the ADC?

That should work.

I imagine they can be used faster as inputs than outputs. You might get above 108Mhz if you have enough drive current. (Assuming the I/O clock can be set faster than 108mhz)

You could perhaps take a page out of rigols book and use multiple ADCs with stepped clocks. That way the I/O is slower and easier for the stm32 to capture and it makes use of the dual-port DMAs


Or just throw a STM32F7 at the problem

[daqq]

Hi guys,

Thanks for the suggestion - I've looked at the FSMC, but could not find some reasonable way to hack it to work with such an external clock - the interface seems to be meant only as a master for memories.

Take into account that the STM32 only has CMOS inputs, no LVDS/CML/ECL/...

Yup, I know. There are ADCs that have CMOS outputs.

Or just throw a STM32F7 at the problem

I've looked into those - it's got most of the same interfaces - and I don't think that it's particularly faster. Did I miss something? I'm open to using them as well

The two or more ADCs approach just complicates things - it's still well outside of the realm of program reading the GPIOs. Reading 2 x 16 bit @ 50MHz seems to me to be the same as reading 1x16 bit @ 100MHz.

[Kalvin]

LPC4370 has a 12-bit 80 Msps ADC. Close, but not quite in terms of bits and speed.

I would consider using a fast ADC with an FPGA as a sample buffer. There are quite a few inexpensive, small pin count FPGA devices available with tens to hundreds kilobytes of fast on-chip RAM allowing 100 Ms/s sampling rate. Using an FPGA as a glue logic between the ADC and MCU makes also selecting the ADC a bit more flexible. The PCB routing should become easier, too. When the sampling buffer is full, you can use whatever bus protocol to transfer the samples into the MCU. Even a simple SPI bus could be usable, if a parallel bus requires too many pins.

Ps. There are also FPGAs with on-chip ARM cores.

[daqq]

I would consider using a fast ADC with an FPGA as a sample buffer.

Yup, that's the current plan. I'm just thinking on how I can get around using an extra FPGA to be pretty much a glorified speed bump.

The LPC looks amazing really - thanks ! I've never heard of such a high speed ADC directly on a CPU. I'll look into it, keep it for future reference, but I don't think it will do.

edit:

Ps. There are also FPGAs with on-chip ARM cores.

Yup, I know - really powerful devices, in BGA packages - I'd like to avoid those as well. Ideally all of it would fit on a 4 to 6 layer board, with a simple technology.

I'm trying to avoid an FPGA for several reasons - partly because we don't have pretty much any in house experience with FPGAs ( I played around with it as a hobby, but other than that nothing), but a lot of experience with ARMs of various sizes. Also, the extra board area and parts, BOM size etc.

The current plan is use a SPARTAN 6 FPGA to do the buffering, perhaps a little prechewing of the data, then talk to it by DMA SPI, get the data out of it, do what is required, then send it away via Ethernet and wait for another trigger event.

[Kalvin]

You could make the ADC+FPGA as a PCB plugin-module with 6 - 8 layers and connectors to the mother board. The PCB size is be quite small anyway, so the board wouldn't cost a fortune and it could be manufactured and tested apart from the motherboard. The motherboard should be simpler, inexpensive 4-layer board. Just an idea.

[Jeroen3]

Maybe you can use SGPIO and the dual core nature of an NXP LPC4300.

[ajb]

Have you looked at Cypress PSoC parts?  I believe you can hook up DMA triggers from within the programmable logic section so you should be able to capture from a parallel bus directly to memory with whatever clocking you need. 

[daqq]

Have you looked at Cypress PSoC parts?  I believe you can hook up DMA triggers from within the programmable logic section so you should be able to capture from a parallel bus directly to memory with whatever clocking you need. 

Thanks, I've looked into them before, but found they had no direct Ethernet support (MII/RMII), and their maximal frequency was 80(?) MHz. The memory wasn't large either.

[mehdijokar]

Hello

I want to read ADC 80MSPS with STM32f429. ( 8bits data parallel )
Is it possible without using fpga?

Thanks,

[daqq]

In the end I used an FPGA. It could have probably worked, but I needed an FPGA to do other stuff as well.

[iMo]

@daqq: that was a long time back I would guess

The FSMC is slow. It is intended for interfacing with various kind of memories. It follows their "timing protocols" and it adds some delays in 1 clock chunks (you may set in the FSMC registers). With 0s put into those FSMC timing registers you get something like 30MB/sec with F407 @168MHz..

[mehdijokar]

Thanks for your response.