Electronics > Projects, Designs, and Technical Stuff
Analog challenge:High power/high speed amplifier for physics experiment
Mazo:
--- Quote from: duak on February 21, 2020, 11:59:15 pm ---Mazo, have you run a simulation of this circuit? What did it tell you about the turn on and turn off times of the output devices? I'd expect the turn off times of the output devices to be a very large part of a 1 MHz cycle. If the CE device (Q1 to Q10) of the output stage saturates, the turn off time will become even longer. If this happems, you'll have to add a Baker Clamp to prevent it.
Stability will be a big issue with this circuit. I would start with trying to stabilize the output loop through R12 first with the overall loop perhaps set to a higher gain.
I almost forgot, since the load is inductive, you will need some clamp diodes from the output to the supply rails to handle recirculation currents.
--- End quote ---
Am I missing something or if the CE devices get near saturation can't I just move the CB base bias supply "further" away and thus add some voltage to the C-E drop and prevent saturation?
The simulation is almost hopeless,time domain simulations are in the ps/s range,and if given enough time they provide some weird ass results like MV voltages and MA currents,the bottleneck seems to be the 2SC5200 and 2SA1943 models.
I have thought about the recirculation diodes,just tried to strip the sim out of everything that isn't required for the operation in an effort to fix the sim(didn't work).Should have a look into the capacitances of such diodes that the DUT will have to swing around,or just put diodes that are say 1A continuosly rated and rely on the fact that the output will have not that much energy stored in it and the diodes will survive the transient.
Working on a new schematic,will post soon.
fcb:
--- Quote from: duak on February 21, 2020, 11:59:15 pm ---Mazo, have you run a simulation of this circuit? What did it tell you about the turn on and turn off times of the output devices? I'd expect the turn off times of the output devices to be a very large part of a 1 MHz cycle. If the CE device (Q1 to Q10) of the output stage saturates, the turn off time will become even longer. If this happems, you'll have to add a Baker Clamp to prevent it.
Stability will be a big issue with this circuit. I would start with trying to stabilize the output loop through R12 first with the overall loop perhaps set to a higher gain.
I almost forgot, since the load is inductive, you will need some clamp diodes from the output to the supply rails to handle recirculation currents.
--- End quote ---
Ooooooh. Baker clamps :-*. Dave should do a video on transistor saturation.
magic:
The common emitter combined VAS/output stage topology you chose has high open loop output impedance and relies on feedback to bring it down to reasonable territory. If you want low impedance "voltage" output, you will need plenty of GBW. Consider removing those paralleled transistors and adding a unity gain buffer stage instead.
If a few % THD is enough, you may get away with leaving the buffer outside any global feedback loop. Try to simulate such an output stage alone, experiment with Darlington and Sziklai pairs. To measure distortion, disable "compression" in LTspice control panel and take FFT of the sim output waveform, the option is there.
duak:
Mazo, I'm not surprised the simulation gave you trouble. I would start with just half of the driver and output stages (Q1 to Q5, U1 to U5 & Q16) with a simple resistive load to understand how they work and how fast they are. I'm not a SPICE user so I can't offer much help there.
Regarding saturation, I expect the simulation to act differently from the real world because the bias voltage of the CB stage is not current limited. This will just make the CB transistor saturate instead of the CE transistor. One way to look at saturation is that when the circuit limits collector current to a value less than what the base current and hFE demand, the transistor's VCE becomes lower than its VBE. This increases the turn off time because the transistor is flooded with current carriers and it takes time for them to be swept out. Why I wouldn't be surprised if saturation occurs is because the op-amp will try to drive as much current as it can into the output stage until the output voltage comes to the correct value. Moving the CB bias voltage away from the supply voltage won't make a big difference although it may shorten the turn off time of the CB transistors by sweeping the current carriers out quicker.
Magic's suggestions also make sense and are certainly worth considering.
T3sl4co1l:
Yeah, nothing crazy, a friend has built amplifiers of conventional architecture (diff amp, VAS, emitter follower) with several MHz bandwidth. A beefy VAS, preferably complementary cascode (compare to conventional, where the VAS load is a passive CCS), and outputs with lots of drive (Darlington with fairly stiff bias?), is the way to go. The VAS in turn might be driven by current mirrors from a single diff pair, or a complementary diff pair with no mirrors needed.
If you're just driving coils, mind you can use less voltage with smaller coils and fewer turns. The 200V range seems... excessive?
Also, note that you need at least as much power dissipation as VAR you want. Probably more like double. A linear amp does not return reactive power to the rails, it's 100% dissipated. And it's dissipated in the worst part of operation (e.g. when the output voltage swings low, the current is pulling down, so the high side transistor has to drop Vcc + Vout(pk) while delivering Iout), so shop for transistors with the widest SOA.
So, if you're talking say 200 VAR, expect to need maybe >400W capacity.
The cascode output stage is alright in some respects, but it's a nightmare to stably bias, and as mentioned, optimizes voltage slew rate which may not be the most desirable here.
--- Quote from: duak on February 22, 2020, 07:46:27 pm ---Mazo, I'm not surprised the simulation gave you trouble. I would start with just half of the driver and output stages (Q1 to Q5, U1 to U5 & Q16) with a simple resistive load to understand how they work and how fast they are. I'm not a SPICE user so I can't offer much help there.
--- End quote ---
Timestep too small (or some platforms will just keep chugging along on garbage (ps/s) rather than terminating) is often a sign of unrealistic circuits, or poor models. Note that .MODEL statements are just that, transistor models, no package parasitics or anything -- you need to add those manually if you want a realistic circuit. And those will be critical in a circuit pushing the performance of the output transistors at least.
Tim
Navigation
[0] Message Index
[#] Next page
[*] Previous page
Go to full version