Hi guys,
I'm designing a BMS around the BQ40Z80 from TI. This chip controls protection MOSFETs in the positive (high-side) path, but measures the battery pack current in the negative (low-side) path. From the chip design perspective I can totally understand why they are doing this, but in my application I just don't have access to th negative power path altogether.
Because this chip literally has no competition at the moment (I have done a lot of research - the only other option is ISL94202 but that's the chip that I had been using in the previous design that I am currently replacing because of very bad results - long story), I have designed a circuit that adds high-side current sensing to it. It works well, but has a precision problem. The two resistive dividers R17/R18 and R19/R20 need to have exceptional precision, and even with 0.1% resistors I get a theoretical differential offset of 0.607mV. This corresponds to 607mA, which is way more than the precision of the involved chips. The INA186 for example is specified for +-0.05mV offset error.
These are the boundary conditions for my design choice:
- the BQ40Z80 wants a common mode voltage at SRP/SRN of no more than 300mV (info from the TI field engineers).
- the maximum current will be +/-100A, which must correspond to +/-100mV differentially at SRP/SRN.
- I have chosen a 300uR current shunt, the INA186 has a gain of 25, and my resistive dividers have a gain of 0.13 approximately.
- I do not have enough space on the board for more components (like, e.g. a buffer opamp).
- current consumption must be minimal, as the circuit is directly powered from the battery.
What is making my head scratch is that I have the impression that there must be a better way to do this, which avoids the need of high precision resistors. The OUT pin of the INA186 needs to be able to produce a +/-0.75V swing relative to its REF input, as that corresponds to +/-100A. This means that the REF potential needs to be at least 0.75V with respect to GND. But the BQ40Z80 cannot accept this voltage at its SRP pin according to the TI engineers. Hence, I have to scale down both OUT and REF voltages, which makes me end up with two resistive dividers and the resulting precision problem.
I hope that I am missing something obvious here?
Cheers Frank