Analysing 500W BTL class D amplifier schematic

[Yansi]

Hello,

seems I finally got another excuse to play with something interesting: Got a four of these rather old and very good active DSP bi-amped speakers, and after almost 20 years, the internet finally gave out the schematic from them. During some repairs in the recent years, I have reverse engineered the complete schematic of the HF amp. This time however, we can finally see the Italian beauty in its fullest, and finally I can get some understanding how they have designed the class D  LF woofer amp. Please find the schematic attached.

 psr212a-psr212am-schematic.pdf (1544.31 kB - downloaded 161 times.)

The most relevant part of the class D design is at page 10 (modulator) and page 11 (power stage).  At first, it did look intimidating, but most of the parts are rather simple and easy to understand, except one that is pictured below.

For others not familiar, to easier orient in the design, I made the following notes:

The input differential audio signal is fed into U5-A (gain is about 0,66) and low-pass filtered by U5-B (~100kHz cutoff). U1-A seems to be the main error amplifier and U1-D seems to be some form of a PI-controller* (see further). Transistors Q4, Q5 make a form of amplitude limiter to about +-2.56V (5.12Vpp, just assuming Vbe of 600mV). This control signal is then split into a buffered (U1-B) and negative (inverted by U1-C) portions. Further (negative only) amplitude limiting is applied to these by means of Q2 and Q3 to about no less than -2.48V (again, assuming 600mV Vbe). This pair of limited signals is fed to a pair of comparators, which produce a PWM signal by comparing with a triangle wave generated by U9-A. PWM signals are then again split into positive and inverted by using the OR and NAND gate (to make matched delays in both positive and inverted paths) and provided to the respective gate drivers (IR2110 on the page 11).

Feedback is provided to the U1-A and U1-D from an output of the power stage. A differential amplifier U4-A, U4-B senses the differential voltage across the load after the PWM is low-pass filtered.

The triangle wave is produced by an integration of a 50% square wave by U9-A. Square wave of 250 kHz is generated by dividing a 1MHz ceramic resonator oscillator by 4, using two T flip-flops. Feedback network R27, R28, C27 provides a stable DC operational point of the integrator, so the triangle is well centered across 0V at all times. The trimmer R53 can slightly tweak the integrator's time constant, so an exact amplitude on the output can be set. Mid-point position of the trim pot seems to provide almost exactly 5Vpp of triangle wave (at mentioned 250kHz).

The part of schematic i am not confident I understand enough, is this one around U1-A and U1-D.



It seems to me, U1-A is a kind-of normal non-inverting amplifier, setting the overall gain of the whole class D to be (1+R46/R43) = (1+47k/10k) = 5.7, multiplied by the gain of the diff-amp U4 (gain of the diff amp is about R34/R35 = 330k/35k = 9.43). The overall gain of the class D amp then should be 5.7*9.43 = 53.7x, not counting the input attenuation of the U5 differential amp. That sounds reasonable to me.

U1-D seems to be a PI controller, with the DC gain set to R14/R11. What is however a bit strange to me is where the non-inverting input of U1-D (pin 12) is connected at: There is a voltage divider R12 R13, providing a portion of the feedback signal from U4. Is it some kind of a feed-forward?

My main question now is are all my assumptions right?
I think this must be some pretty standard class D modulator topology, however I was unable to find anything about it. I am only familiar with the single-ended Philips-patented self-oscillating thing (with feedback after LC filter) and the single-ended "IR audio amp" scheme using the self oscillating second-order integrator (feedback before LC filter). Do you know about any application notes or papers describing this topology and its design in detail?

My intention is to try to build a class D like this for some other application, hence trying to understand the design fully.

So far I have simulated the triangle generator, as I was confused by the weird feedback components R27, R28, C27 and simulated the feedback differential amplifier, that senses the voltage across the bridge tied load (i was doing a dumb mistake when trying to analyze it on paper, using just math).

[Yansi]

Okay, I have made some progress with the simulation. I successfully made the class D amp run in the sim. You can try yourself, sim is attached in ZIP file below this post.

 FBT_PSR212a_modulator_sim.zip (4.15 kB - downloaded 58 times.)

Here is the simulation schematic. Lazy me replaced the power stage with the programmable voltage sources (BV) to drive the outputs. Everything seems to work about fine. (Note all component ref designators below will be those from the sim schematic.)



But I still could not figure out, how to derive the analytical formula of the overall gain of this thing. What I know for sure, is that the differential feedback amplifier U5, U6 has attenuation of 35k/330k = about 9.43x. Overall gain measured in the simulation seems about 32.5x, as for 1V input the amp produces about 32.5V on output.

The transfer of U8, the first opamp directly at the input, seems to be:
V(input)*(1+R20/(R21||R22)) - V(FB)*R20/R21 = V(input)*2.2127 - V(FB)*0.2127

That seems to be all right, if tested in a separate sim. However, the additional PI controller stage U7 has feed-forward path via R24 R23, which causes the overall gain to change. Removing R24, R23 and grounding the U7's non-inverting input leads to a gain increase and the gain is then about 92x from input to output. That kind of makes sense: 92 / 9.43 (gain of the diff feedback amp) leaves about 9.76x for the input opamp. See the U8 transfer func of 2.212*4,7 = about 10x. As the over gain of 92 is an approximate cursor read from the sim, it seems plausible.

But I am now out of ideas, how to analytically calculate the gain with the R24, R23 feed-forward path present. Any ideas please?


//EDIT: With the feedforward path via R23 R24 to U7 disabled, the gain seems to follow well the gain set just by U8, assuming output of U8 is close to zero (which it almost is, due to moderate openloop gain of U7 (29x) and the PWM modulator (90V/2,5V = 36x) or 29*36 = 1044 total openloop gain there).  The overall amplifier gain is then:
Gv(input)*Gv(feedback)*Gv(differential_amp) = (1+R20/(R21||R22)) * R21/R20 * R16/R15.
Oooomph. But now with the feed-forward? Just how?

[Yansi]

Seems I may have figured out the closed loop gain formula. However, still not fully sure, my colleague today tried to look at it and we both do get slightly different results. No idea if any of us still has a mistake somewhere or just number rounding during manual calculation.

This seems to be the closed loop gain (component refdes according to the simulation schematic):



Even if this may be accurate enough, there are still a lot of unknowns to investigate. For example the purpose of the various amplitude limiters used in the original schematic, especially the two negative amplitude limiters Q2 Q3. Need to look at those next.