Any idea about IC design?

[blueskull]

Hi,

As my audio DAC project going well, I came up an idea to put the messy analog and mixed signal parts into an ASIC, to be precisely, the biasing network, switched cap DAC, some simple digital logic and a passive current filter. After doing this, the solution can be simplified to only a DSP, an ASIC and 4 dual OPAMPs.

I have simulated SPICE schematic, and a simple and crude prototype, and now how can I put them into an IC?

I am currently using 2.5V AUC logic, but I can surely accommodate 3.3V logic, so can I use 0.35um process?

What kind of EDA tools do I need? The most expensive one I can afford is Tanner tools, for higher levels, I can not handle the price.

Are there any step by step books on ASIC designs? Are there any blogs or forums about this?






Regards,
Bo

[free_electron]

That doesn't work...

you first need to identify the technology you will use, get the design-kit ( the parts library with attached spice models )

then you can start your design. whatever you have done so far is useless as it was not done for the technology you are going to use.

Tanner EDA is the cheap solution. anything else costs millions. ( Cadence / Mentor )

But first : you need to find someone willing to take in your design.

for one-offs CMOSIS is a way to go. you can charter a corner of a wafer.

[Alex Eisenhut]

Can't you talk to a local EE department at your friendly university?

I think McGill here in Montreal goes through these guys

https://www.mosis.com/

I worked for a startup that made their own ICs but this was a few years ago. Perhaps the situation has changed.

[filssavi]

I'm really afraid I have to spoil your dream,since if you have to ask a question such as "how is it done?", then you don't have the knowledge and experience to do analog IC design, the major hurdles you have to clear are:

1) have knowledge in integrated Analog design, since it's a totally different beast from normal board level design", to give you an example (without using uber-expensive  optional process steps) passives (resistor, Inductors and Caps) have a + o + 15/20% tollerance from nominal value on a per wafer basis (every resistor/cap on a single wafer has the roughly same skew from nominal value), moreover high capacintance and resistance value are difficult to get and will cost a lot of money (either in term of area or expensive optional process steps), you have to be familiar with sub-treshold/weak inversion design (if using CMOS tech) to get high gain devices
2) if you already have experience in the field (and is highly unlikely since if you had you wont be doing this questions) now you have to get the right tools for the job and let me tell you it ain't cheap, cadence IC platform (virtuoso, spectre and all) that's the industry standard that everybody uses does cost roughly half a million$ so most likely out of your reach, Tanner EDA thet is far cheaper, that said it's around 20.000$ a seat so not what you would call cheap (not in the absolute sense) and you have to keep in mind that Tanner doesn't have such a good  foundry list as other tools
3)now that you have your CAD tool you need to get a PDK (process design kit) that will have all the models for the simulator and the rules for the DRC, it's usually free but it may not be easy to get it as a private indvidual (IE. not a company)
4)good now you that you have your EDA tools, your manifacturable design, we need to talk about verification, IC manifacturing is very expensive and time consuming (from tape-out you need to wait 3/6 months to get your IC's) so you don't want to screw up a run with a bug in the silicon since it'll require a lot more time and money, for this you need to do simulation,the most important is the post-layout one, you will need to extract all the parassitics (resistance, capacitance and so on)  with a dedicated tool (you guessed it, it costs a lot of money) and simulate your design once again to see that it will still work, if not it's back to the drawing board
5) ok now you have a manifacturable and tested design, we're almost there you just need to get your desing produced, and here we have another problem, It's f****g expensive, even using services as MOSIS, that aggregate multiple designs on a single wafer, you are looking at a multi-thousand $ kind of order, for just a few parts


Bottomline, if wou don't have a precise need for an ASIC (IE. it can't be done in any other way) go with another solution ( FPGA or commercial), it'll be cheaper and most likely have much grater performances

[amyk]

The OP is in China. I'm pretty sure there are ways to get it done cheaper there, although if he knew, he wouldn't be asking here...

I've come across a bunch of Chinese forums on IC design, here's one: http://bbs.eetop.cn/?gid=57

[filssavi]

Well of course there will be, but having cheap foundry and pirated EDA tools, doesn't make it any easyer, in fact the eorst part is the design itself, and if OP is asking here (not even a more specialized ic design forum), and tge fact that he is asking all together, make me think (iI stand to be corrected obviously) that he doesn't have a clue about IC design, the only fact that he's trying to design a mixed signal IC (notoriously the hardest one, since you have hard switching signals with fast edges and a pulsed current draw, and noise sensitive (hi-fi audio) analog circuits nearby is not ideal

Then also going cheaper on the fab side also means going lower quality, so he could have non working dies form the foundry either because of a design errore or a foundry problem, that did, t got caught by QA (if they even have one, which for the extreamly cheap ones i highly doubt)

My advice is look at a board level solution, since is by far easier to design, test, debug (you cannot debug a chip when it's packaged, you have to do it on the bare die with specialized equipment), and if you're really interested in analog IC design, then look into getting a formal education, with someone that is competent, and into the businnes

[filssavi]

Ok it's not as bad as I thought, since I see you aren't some kind of troll or worse audiophool DIY "i can do it better" kind of nut 

there are still a couple of issues
- the technology, as you probably are aware, sub-micron design is much more challenging than above, since the classical model for the MOS transistor doesn't hold any more (well it really start to fall apart at 1 um already) and since we are in highly scaled devices kind of world and here lies the problem with the tools you want to use, the problem is that between classic MOS model and real device there start to be 20-30% difference, and this depends quite badly on the process used, so to cut a long story short you will need to use a PDK, and the problem with Electric is that no one uses it (for real ic manufacturing at least), so foundries will not put effort into building a dev-kit, nor into testing a ported one.
-the second issue is that you to be aiming at a mixed signal IC, with a DSP, DAC and analog, and this is a pretty big system,  the worst part is that having digital on die, is creating you much much more problems than it solves, think at mixed signal pcb design problems, well the one's you'll be facing will be pretty much the same, just on steroids, since with smaller distances you'll get much greater coupling between nodes of the circuit, and here is where post layout sim will be handy, you might have some coupling between a clock line/digital singnal and an analog node, and you wont see it until you get your IC fabbed, and it get's worse, it might be that the problem is only in certain units, or worse in all the units but in some specific operating condition (Vdd, Temperature, load etc) that might be impossible to catch even with thorough testing

as for QA I wasn't thinking about csutom test jigs, but a more basic testing that every reputable manifacturer will do on every wafer, in the gaps between 2 dies they will place some test dispositives (resistors, capacitors MOS and so on) they will then test them, and if the value of the key parameters(resisance/square, capacitance and so on) is outside of the range between plus sigma and minus sigma from the mean value, then the wafer will be rejected, and you wont see it, if you decided to go to a crappy chineese low cost fab, to get better price they may skip this test and send you wafers with ultra bad  performances


So if you are still interested in doing this, the first thing is to use a commercial EDA package (be it tanner or cadence), I'm afraid you cannot escape it, if you want to use advanced tech ( 0.35 is still pretty advanced for a low frequency analog design)..
let's talk about the technology now, you will probably need 2 or 3 options as basic (digital version) cmos process probably wont be enough, the first and foremost is the High Resistivity Poly resistors, and PIP (poly-insulator-poly) or MIM (metal-insulator-metal)  capacitors this two options will give you linear resistors and capacitors suitableto analog circuits, you'll probably need also thick oxide transistors if you want 5V compatibility, since core devices go only up to 3.3V (at least in the 0.35 AMS process i used, but I think it's a pretty common thing)

now with your process sorted, we can think about the actual design of the thing, the best would be to split the digital part and put it in an FPGA (or board type of solution with discrete dac and stuff, depends on what you need to do), and do an analog only IC, that will give you much less problems, I would stay away from switched caps as long as you can, and use Ratiometric circuits instead (the ones that does depend only on the ratios of two values) since  you'll have very very small mismatch between devices on the same diem, think it this way, Op-amp inverting amplifier, is safe because [R1=10K, R2=1K] or [R1=12K R2=1.2K] is the same, what is not safe are thing like passive filters since they depend on the absolute value of a component, another technique might be to put critical passives on the board, instead of integrating them, since 0.1% SMD resistors/caps are quite cheap, the choice is not without disadvantages though (more pins are needed and different temperature coefficients).

The filter cannot be integrated, not a passive one at least, you could opt for an active one instead though, for the dac I would suggest using a switched courrent source one, since courrent mirrors are extreamely cheap and easy to make( you'll want to use a wide swing cascode mirror), swithced caps circuits are not

[rfeecs]

5. Are there any hidden costs in designing an IC? I design it myself, so no labor cost, I use open source tools and avoid patents, so no IP costs. I have access to bonding and packaging process, so no packaging cost. Are there any other costs besides MPW service cost, PCB cost, learning cost and shipping cost?
...
I would try doing it with no external help, and with as low cost as possible, since this signifies a revolution of what a hobbyist can do.

How much are you expecting to pay for the MPW run? $1,000?  $10,000? 

I don't think many hobbyists would be willing to spend that kind of money, unless your ASIC can mine bitcoins or something

How is this a revolution of what a hobbyist can do? 

[rfeecs]

rfeecs,

The MPW run on a 2mm by 2mm chip costs only 2886 USD, and considering a MSEE makes 8k+ USD/mo, assuming one only tape out one design per half year, the cost is only $481/mo, or 6% of the total income. Even paying 35% income tax, it is only 9% of total income, which is much cheaper compared to other "high end" hobbies.

I know many MSEE ASIC designers (including myself).  But I don't know any that would want to tape out ASICs as a hobby.  Actually, few are interested in electronics as a hobby.  I guess I just hang out with the wrong crowd.

For 2mm by 2mm I would have expected more like $25k.  I guess you have found some truly cheap alternatives.

[amyk]

Europractice's MPW price list: http://www.europractice-ic.com/docs/MPW2015-general-v3.pdf

Looks like the cheapest at the moment is AMIS 0.7u at 360 euro/mm^2.

The smallest processes get significantly more expensive, but theoretically you can also fit much more circuitry in the same area, so it sort of balances out. 0.35u costs twice as much but can theoretically be 4x denser, so maybe that makes it good value for you.

Globalfoundries' 28nm process costs 9390 euro/mm^2 but that's 625x denser than 0.7u...

[rfeecs]

Does it add up?  20mm x 20mm reticle, so for 2mm x 2mm you are taking up 1/100 of the reticle.  For $2900 that's $290,000 for the mask set and processing one wafer.  I guess it's do-able for a 15 year old process.  No way for a modern process, but of course those are priced higher.

Still, too rich for my blood. 

Seriously, you should take advantage of whatever free tools and services you can get from your school.  You really need to use Cadence.

[filssavi]

The AMS process you mention (C35B4C3) is the same we use in our university, and i can confirm that is an analog process (i used it in my analog ic design  course to design an opamp and a bandgap reference

Ok since you want to do a delta sigma, switched cap filter and all will be  ok,  for the reference it depends on how stable your temperature and supply voltages are, since might be handy to include an on chip ban?gap viltage reference, but if you want absolute temperature stability then of chip is the way to go

As you don't  have the budget for a second run, i still advice you to use cadence, this is already a big project, and i don't think you're going to make your life easier using crude tools, and moreover, by using it you'll be getting experience that will be usefull if you 'll ever want to do analog IC design

As for books, I used razavi's analog CMOS integrated circus

[filssavi]

For Iref you don't need to go off chip, one you have your bandgap voltage you can derive a current from that (you basically need to use the voltage as a reference for an opamp that controls a transistor that in turns feed an appropriately sized current mirror to get the reference current you want, the principle is that of this schematic:

http://1.bp.blogspot.com/_Gky8ltNWVFk/SciIvGRCtYI/AAAAAAAAAZg/fd8RfJu8FK0/s320/4-20mA+source+06.gif

you just have to use your bandgap instead of the diode, since you have a NMOS transistor the base resistor can go, and lastly the higher resistor can be swapped with a current mirror to distribute your reference (use a cascode for higher output resistance)

MIM and PIP capacitors are fundmentally different beasts 

MIM capacitors are free, since they use the Parassitic capacintance between 2 or more metal layers (the maximum density is reached with a 2D finger pattern on multiple metal layers), the disadvantage is that since the field oxide between metal layer is thick they have less capacitance per unit area

PIP capacitors, are instead formed between the gate poly layer and another layer Epitaxially grown just above (this is an extra optional litho and etch step so it costs money), the upside is that they have a thinner oxide and you can get higher capacitance

MIM caps have also a lower parassitic capacitance to the bulk , since they are further away from it (with respect to PIP capacitors), so in HF applications this could be an issue (i think we are talking about tens or hundreds of MHz so don't know how much it does apply to you)

another type of capacitor that you could use is our old friend the MOS Structure, this is just a standard PMOS with source, drain and bulk all connected, and used in accumulation region, in theory you could use an NMOS, but there you would have the problem of the bulk, the AMS process we were talking about doesn't have triple well, and so you have the bulk of the nmos connected to all the others, and since all other moss have bulk connected to ground, you need to connect the bulk/source /drain of the NMOS capacitor to ground to avoid shorts, the downside of this cap is highly non linear with the voltage applied, so use it only where this can be tollerated

50pF are quite a lot to integrate on an IC, i'm afraid, so i don't know if MIM are enough (you might find that the increase in area for the cap is more expensive than the PIP option) or you need PIP

[jwm_]

Don't forget magic, it's how i learned VLSI design at Caltech and i belive is still used to teach there.

http://opencircuitdesign.com/magic/

It's pretty fun if you are into the nitty gritty of how CMOS works and get your chip fabbed.

[bzeng]

Don't forget magic, it's how i learned VLSI design at Caltech and i belive is still used to teach there.

http://opencircuitdesign.com/magic/

It's pretty fun if you are into the nitty gritty of how CMOS works and get your chip fabbed.

Seems magic is also a great tool. The reason I chose Electric is because:
1. It was a commercial tool, so it was and is designed for ease of use, rather than bleeding edge experimental algorithms, which I don't need at 0.35 process.
2. I've never played with Tcl, so I prefer a script free tool, and that is another reason why I don't use Cadence tools (Electric also uses script internally, but with proper libraries, I don't need to write scripts myself. This is also exactly the reason I use Altium instead of Eagle).

Still, it seems some modules in magic, such as IRSIM, worth to be tried, and I will certainly use multiple tools while the main tool will be Electric.

Hi blueskull,
Have you succeeded in making your custom IC? Does the software Electric work with the MPW foundries? I also want to make my own IC as an individual. Your experience would be helpful to me.
Thanks,
Bin

[rfclown]

I have very limited experience with ASIC design, so I can't really offer you much help. I only designed a few circuits in early 2000, CMOS and SiGe BiCMOS. But from my limited experience, I suggest:

1. Like filssavi stated " use a commercial EDA package (be it tanner or cadence), I'm afraid you cannot escape it". I can only speak from my limited experience working on projects that used Crolles (I guess ST now?), Jazz and IBM. Maybe things are different now, but in my time the foundries we deal with wouldn't talk to you unless you had the proper tools that used their PDK. I heard talk about them not accepting acedemic jobs because of tools (insufficient DRC etc). Before you start designing, may sure you have a foundry that will accept it with the tools you are using.

2. Find another place besides this forum to ask questions. I don't believe that there are many like filssavi here (I could be very wrong). When I did some ASIC work, I was working with a group of seasoned ASIC designers at Motorola. So when I did a DRC for the first time and it printed out a novel, I had people to turn to.

So I would be looking for a forum (or other groupl of people to ask questions to) that has specifically gone the same route that you are asking about: how to do an IC with cheap tools. This may in itself narrow you down to one process at one foundry using a specific tool set. I would only go down a route you know someone else has gone down before you.

[SiliconWizard]

You'd need to tell us what is so special about your design that it would justify designing an ASIC for this. Even with "low-cost" tools and MPW, it's going to cost you A LOT of cash.
And if you have little to no experience with this, the first run is likely not to fully work as intended. So count at least a second one.

[mawyatt]

Have considerable experience in this field, having created and taught 2 graduate level RFIC courses as an adjunct, and developed a number of ICs in bipolar, CMOS, SiGe, SiGe BiCMOS and InP. Follow the advice of rfclown and SiliconWizard, as most leading foundries are Cadence based with their PDK kits, although we did use Keysight ADS for the InP work since this was what the PDK supported.

Cadence was available to our grad students, so you might consider collaborating with a local university to gain access, or become a grad student. As mentioned plan on spending some serious $ developing a chip, even a simple chip in a rudimentary process. Awhile back TSMC made the baseline 65nm CMOS process available to selected universities on a free or low cost use basis, so you might look into this.

Anyway, good luck with your IC endeavors.

Best,

[bzeng]

Hi rfclown, SiliconWizard and mawyatt,
Thank all of you for your replies, they are very helpful to me. I am trying to develop an IC for cryogenic applications, and I already have a working prototype made by discrete transistors. I don’t have IC experience and I am doing this on my own. Going through the discussion, it seems that collaborating with a local university is my best option.
Thanks again,
Bin

[rfclown]

When I posted my reply to this thread, I had no idea that it was from 2015. Would be interesting to hear what the OP ended up doing.

[Terry Bites]

Will it out perform a commercially available part- the investment will be huge.

[magic]

When I posted my reply to this thread, I had no idea that it was from 2015. Would be interesting to hear what the OP ended up doing.

FYI OP is banned and all his replies deleted. IIRC it went nowhere.

[uer166]

When I posted my reply to this thread, I had no idea that it was from 2015. Would be interesting to hear what the OP ended up doing.

FYI OP is banned and all his replies deleted. IIRC it went nowhere.

Damn I keep noticing random people being banned like Legacy and now Blueskull, I suppose too spicy posts for a forum? (apologies for off-topic).

[magic]

Sometimes you have to choose between spicy posts and a big chunk of Western audience, losing productive contributors either way.
Plus he was being a bit excessive, I think, and never knew when to quit flaming.

[Gyro]

His insistence on all of his posts being removed from the forum was also responsible for this weekend's accident as Dave tried to delete them, and loss of many other peoples' posts / threads as I understand it.