No idea where they get 1mA from, CD4000 gates at 10V are about 600 ohms output, or about 15mA short circuit and decreasing towards the rails.
IRF740 is about 15nC over the Miller step, for a typical load and voltage swing; from 10V that's 1.5nF equivalent capacitance. (The instantaneous capacitance is much higher, because of how Miller effect works.) 600 ohms * 1.5nF = 900ns, about a microsecond.
Probably similar for the 2N6763 and a bit slower(?), but it's so old they didn't even rate it in terms of Qg so it's hard to say. They do give switching times at R_G = 4.7 ohm; at 600 ohms it would probably be closer to 12.7us (using the same method for IRF740, gives 1.8us).
Note this is just for the largest part of drain voltage swing, but also weighted towards the bottom (low Vds), where Cgd is largest. The capacitances are varying all throughout this process, so you can't draw a straight line through anything and say that's the answer.
Because Vgs isn't varying exponentially like it would for a constant capacitance, the gate voltage timing differs for rising and falling edges, and for reactive loads (capacitive loads draw lots of drain current when the drain voltage is changing rapidly; inductive loads drop lots of drain voltage when drain current is changing rapidly). And in turn, drain voltage.
A precise answer is basically up to measurement, or simulation, given a sufficiently accurate model (which isn't always the case from the manufacturer).
Because of this, the design process for MOSFETs uses a guard-band approach: if we need a certain rise/fall time, then use Qg(tot) / Vgs(on) = Ceff, and the driver resistance (or current), to determine gate rise/fall time. Drain rise/fall will be about half that figure.
Tim