LTspice Problem with AND-Gate

[Guy-from-Dresden]

Hello everyone!

Im simulating a small logic circuit with 4 Power-Good signals,
if they are all in Ok state, i start my device.

The problem is, simulation does what i expect but the Output of the
4-AND Gate is only 1 Volt as High Level althogh the system voltage  is 3,3 Volt.

So i did some resaerch to the logic gates in LTspice, and I didnt have to provide
Supply-voltage to the Logic Gates, so this is not the cause ..
Maybe some Gentleman in this Forum got a idea whats the failure.

Kind Regards, Guy

[Guy-from-Dresden]

Okay here is the Input/Output Diagram

One signal is 1,2Volt i switch it with a Komparator to 3,3 -- but in the
simulation i measured the 1,2 Level ...

[Guy-from-Dresden]

So here is my attempt to isolate the Problem.
I just tested the Logic Gate ...

[moffy]

If you look at the LTSpice help file under "LTSpice/Circuit Elements/A. Special Functions' you will find a full description of the logic gates and how to modify their voltage and yes the default behaviour is 0V to 1V logic.

[ArdWar]

LTSpice logic gates are crude behavioral model that simply output the ideal logic operation. It does not simulate the actual logic gates.

If you want it to behave a certain way you need to set up its internal parameter. For example Vhigh and Vlow to change the output logic voltages.

[Ian.M]

To elaborate on Moffy's the answer is in the help file reply!
Goto 'LTspice Simulator' => 'Circuit Elements' => 'A. Special Functions', and read (just above the first table):

... The gates default to 0V/1V logic with a logic threshold of .5V, no propagation delay, and a 1Ohm output impedance. Output characteristics are set with these instance parameters:
<snip table of output parameters>
...

There are more (non-output) parameters detailed in the text after the table.

At a minimum, you will need to set Vhigh.  You should also set Td and Trise realistically, and also tripdt to less than Trise/2 to avoid the simulator ignoring Td and Trise.  It can also be useful to set Rout.

It can be helpful in multi-gate complex logic to use Ref. (or Vt and Vh for Schmidt devices) to set the input threshold independently from the output levels to implement level translation.  This lets you have a 'layer' of input gates or buffers with input characteristics comparable to the real logic you  are simulating, that translate down to  LTspice's native 1V logic levels where you only care about Td and tripdt, then for output signals, use gates or buffers with Ref set to 0.5 and the desired output characteristics to translate back up to 'real' logic levels.

These parameters need to be added as a space or comma separated list to the end of the component line of the SPICE netlist.  To do so from the schematic editor, see Help:
'Schematic Capture' => 'Editing Components' => 'Super Expert Mode'
I usually put them on the 'Value' and/or 'Value2' attribute line, and at least initially, to avoid confusion set those lines as visible!  You can also use the 'SpiceLine' or  'SpiceLine2' attributes as ArdWar showed.  It matters not, as they all get concatenated with spaces between in the netlist. Don't add them to or before any attribute line that has something other than parameter=value pairs on it.
 
I like to set parameters common to all logic in the schematic on one of the attribute lines and gate specific parameters on another so I can simply copy/paste the common parameters from one gate to the next.

[Guy-from-Dresden]

Ok thank You all

[Guy-from-Dresden]

Yeah sometimes is reading the ducomatation a good idea :-D
But I have to say that the configuration options on DC-sources in LTspice
is much user friendly.
Aniway - its free program