Arachne-pnr: an open-source place and route tool for Lattice iCE40 FPGAs

[mian2zi3]

I wrote an open-source place and route tool, arachne-pnr, for the Lattice iCE40LP/HX1K FPGA, building on the awesome work by Clifford Wolf and Mathias Lasser of the IceStorm project reverse engineering Lattice iCE40 FPGAs:

https://github.com/cseed/arachne-pnr
http://www.clifford.at/icestorm/

Support for the 8K is on the way.  Along with Yosys, the open synthesis suite, this gives a fully open-source Verilog-to-bistream FPGA development tool.

http://www.clifford.at/yosys/

The design is pretty straightforward.  It uses simulated annealing for placement and has a congestion-based multi-pass router with A* search.  The main missing feature is timing-driven routing, which I plan to add once IceStorm documents the chip timing.

I'd love to target other chips if anyone wants to reverse engineer them.  :-)

edit: typo.

[clifford]

I made a video demonstrating the flow:

[nctnico]

No VHDL support?

[mian2zi3]

No VHDL support?

Synthesis is done through Yosys.  I thought Clifford would chime in since he wrote that.  Yosys only has native Verilog support, but it does have support to read VHDL by calling through to vhdl2verilog.  I refer you to the documentation for the Yosys vhdl2verilog command:

http://www.clifford.at/yosys/cmd_vhdl2verilog.html

If someone wanted to contribute a native VHDL frontend, I'm sure he'd be thrilled.

[free_electron]

just out of curiosity : why ?  ( because we can, or, out of curiosity , are valid answers )
why go through all the trouble trying to roll your own synthesizer and mapper.

anyway, looks like lattice have sprouted a whole family of interesting devices. some in qfn some in 16 ball bga's with relatively large gate counts , at low prices ( atarting at 1.5$ per piece )  time ot take another look at these...