Dummy load, MOSFET power ratings, and cooling

[pstemari]

I'm reading through the various dummy load topics, and looking at some datasheets to pick a MOSFET.  The MOSFET power ratings don't seem to make much sense in conjunction with the thermal resistance values and maximum junction temperatures given.

For example, the IRFS7530 in a TO-220 package lists max Rds(on) 2.00mOhm, max Id of 195A, and max Pd of 375W.

Sounds great!  I should be able to test a 30V, 10A power supply with one of these, yes?

Here's the problem.

Read further in the data sheet, and you find the max junction temperature is 175 deg C and the thermal resistances for junction to case and case to heat sink are 0.4 and 0.5 deg C/W.  Total thermal resistance is then 0.9 deg C/W and at the max Pd of 375W, you get 337.5 deg C temperature rise.  Subtract that from the 175 deg C max junction temperature and you find that the heat sink needs to be kept at -162.5 deg C, aka 110 deg K.

That's colder than dry ice, although liquid nitrogen (77 deg K) could work.

I mean, seriously?  They rate the thing as if the heat sink is kept in LN2? 

There's some better package options than the TO-220--the TO-262 can get the thermal resistance down to 0.6 or so, but I don't see any options for something like an old-style TO-3 or a stud-mount that might give you a bit better power dissipation.

Am I reading the sheet wrong or is the listed rating bogus?

[rob77]

if you're aiming at 300W then forget TO-220, rather desig your load with 4 (or even more) paralelled TO-247 mosfets.
and dont forget the thermal derating - values like 2W/degree celsius are not uncommon (300W mosfet becomes a 100W @ 125C regardless of the cooling) - check the datasheet carefully.

[pstemari]

Right, TO-247 is what I should have mentioned above as the alternative.

So in other words "375W" is complete and total puffery.  The TO-247 package at 0.6 deg C/W junction-case-heat sink is a bit better, but still, 300W is a 180 deg C rise meaning the heat sink would have to be kept at sub-freezing temperatures.

Sears has pulled this sort of bovine excrement for years with their bogus horsepower ratings, but I didn't think it had spread to electronics datasheets.  Sigh.

[richard.cs]

375W is based on the junction-case thermal resistance, it's the number you'll get if you keep the case at 25C. Case to heatsink depends on mounting method and I'm rather surprised they mention it in the datasheet. 0.5C/W is quite high for case-heatsink and I suspect you can do better than that. You will not keep the case at 25C whatever you do however. 

Since, attempting to actually get 375W in a TO-220 is unrealistic, multiple paralleled devices will be needed. You should also look at the DC curve in Figure 10. You'll see it can do (with 25C case temperature!) 2V at just under 200A and something around 7V at 60A, that's your 375W, now look at the regions both sides of that diagonal line between those points, this is your 375W line. Once off this line you to either end can't do 375W anyway even at 25C case temperature. To the left at the LV end it's limited by the current in the legs and bondwires, to the HV end it will be limited first by second breakdown then finally (the right-hand side of the graph) by the 60V maximum Vds. At 30V it's limited to 0.8A DC anyway, it won't even do 10A for 1ms at 30V! :-(

I suspect this is a poor choice of mosfet for your application, but you should look at the safe operating area graph for any mosfet you intend to use. Modern fast-switching mosfets do suffer from second breakdown, just less so than bipolars.

[Mr.B]

I am currently designing a DC Load using the IXTH30N50L2 (To-247 case)
The SOA is 200W @ Tc=75C
As others have suggested, using multiple devices is the best way to go.
It is my intention to build a 1200W load. To do so I will be using 12 of the above devices in a water cooled solution.

[T3sl4co1l]

Yeah.  Somewhere there's an appnote describing the type of test setup they use to measure dissipation -- it's something like, nucleated boiling freon at 25.0C.  Meaning, not only is it refrigerant under controlled temperature and pressure, but they're actively stirring and frothing the stuff, so that if the teensiest, least bit of energy flows into the liquid, the already-seeded bubbles expand instantly, absorbing that heat as phase change.

Or to put it another way,

When they say "case" temperature,

They mean the whole case, and they mean Twenty Five Celsius.  Period.



Useless?  Oh, you have no idea.  But, apparently everyone does it, so...


Much more realistic numbers are 50W for TO-220, 100W for TO-247.  And that's still being rather generous, assuming very thin insulators (or none at all, just grease), with semi-realistic heatsinking (generously sized for convection, or a cake walk for water cooling).  With simple heatsinks and Sil-Pads, more like 20 and 50W respectively.

So, yes.  Quantity is your friend here.  The overall size of silicon used in a device hardly matters; you do need a big enough die that it doesn't burn itself up from 2nd breakdown (which IS a thing with MOSFETs, now that they're as power-dense as only BJTs used to be).  You can shop for "Linear" FETs (IXYS makes them, and a few others), or just keep flipping through datasheets until you see a DC SOA big enough (if they only go down to 10ms and not DC, keep reading!*).

*Strangely... most manufacturers of IRF740 do not provide a DC curve.  For instance, the current issue Vishay/Siliconix sheet does not.  The ST datasheet, issue June 2002, does, but this was removed in the August 2006 ("obsolete") issue.

From my own testing, the Vishay/Siliconix device has a DC SOA substantially beyond what it says (either RthJC typ. is half what the max. says, or Tjmax goes over 200C!), and the silicon die inside is quite generous given the device ratings (easily 3 or 4 times a comparable 'new design' transistor of the same ratings), while costing the same price -- or less.  (Which just goes to show you how much cost goes into making the masks and NRE and everything, and how little goes into the silicon material itself.  It's that cheap to just keep on cranking the same damn part, 30 years later!)

But yeah, as for loads, either use a massive number of transistors, or ballast it with resistors.  I designed a nicely featured one for a battery reconditioning company; I'll drop in a link when we get some press release action going.  (And hey, if there's enough interest, that's always nice to speed things up.. )

Tim

[Mr.B]

Hi Tim,

I would very much appreciate a look at your design.
I am in the middle of designing my own load as mentioned above.
Being my very first power electronics design, I am treading very carefully.

[Jeroen3]

After a long time searching for an affordable and available mosfet. I've found an IXTQ 22N60P, which will easily do 150 Watt with 40V max, the heatsink will be hot though. Notice fets are damaged by voltage, not by current.

[nctnico]

When using a mosfet or transistor in the linear region the safe operating area graph is very important. Typically a device intended for audio or linear applications will perform much better in a DC load than a device intended for switching.

[rob77]

After a long time searching for an affordable and available mosfet. I've found an IXTQ 22N60P, which will easily do 150 Watt with 40V max, the heatsink will be hot though. Notice fets are damaged by voltage, not by current.

actually mosfets ARE damaged by current - heat is produced by flowing current and heat is able to damage any mosfet easily.

damage by voltage is less common if you have a gate protection (to avoid Ugsmax) and some kind of snubber circuit to get rid of Uds voltage peaks.

[Jeroen3]

If you have an overcurrent situation, there will be a chance of thermal runaway.
If you have an overvoltage situation, the fet will be destroyed almost immediately.

[Jeroen3]

PSMN1R5-30YL looks like quite nice @ approx USD1.30 but only a low of 30v

You will need to maintain device mounting tab at 25 C to keep that soa, it's quite bad using this switch mosfet for linear stuff.
The Rth(j-mb) is 1 (Fig 5. 100% duty cycle) then Fig 2 will tell you that at 50 C mounting base temperature, you're at 80% of 109 Watts.
Convection of the footprint/heatsink isn't used in the calculations yet. To keep the device at 50C, while putting in the 80%, 87 Watt, you will need an <0.5 K/W heat extraction of the mounting base. Excluding the transfer loss.
That will be a ceramic or aluminium substrate PCB.

During characterization it's done with a device linked below, with almost infinite cooling for this tiny device.
http://www.atecorp.com/products/temptronic/tpo4310a.aspx

[nctnico]

If you have an overcurrent situation, there will be a chance of thermal runaway.

No, a hotspot will develop and the mosfet gets destroyed immediately.

edit: the current is not spread evenly over the die. Some areas will conduct more current than others. In an overcurrent situation the areas which conduct most of the current will get the hottest which will destroy the mosfet when a device is operates outside it's SOA. I have killed transistors rated for 1000W by letting 2A flow with 50V across the transistor.

[DanielS]

375W is based on the junction-case thermal resistance, it's the number you'll get if you keep the case at 25C.

It is much worse than that: the ridiculously high power figures on MOSFETs are usually for 10µs non-repetitive pulses. The junction needs to be allowed enough time for heat to spread out from the junction before another 375W dissipation pulse can be applied. When you increase pulse width to 1ms, the SOA drops to 100-150W, and when you go all the way to DC, you end up with only a ~75W SOA even at 25C T_C for TO220 devices. Most TO220 MOSFETs I have seen are not even specified for DC SOA.

If you want MOSFETs with high DC SOA in a convenient package, you might want to look at TO-3P devices instead: these are often specified for 125-150W continuous.

[rob77]

If you want MOSFETs with high DC SOA in a convenient package, you might want to look at TO-3P devices instead: these are often specified for 125-150W continuous.

TO-3P is basically the same package as TO-247. but anyways... i wouldn't go higher than 70-80W continuous with those packages.

[David Hess]

If you have an overcurrent situation, there will be a chance of thermal runaway.

No, a hotspot will develop and the mosfet gets destroyed immediately.

edit: the current is not spread evenly over the die. Some areas will conduct more current than others. In an overcurrent situation the areas which conduct most of the current will get the hottest which will destroy the mosfet when a device is operates outside it's SOA. I have killed transistors rated for 1000W by letting 2A flow with 50V across the transistor.

This behavior is not widely advertised for obvious reasons.  Most datasheets show a straight line along the power limit of the safe operating area curve.

At low voltages, power MOSFETs are self ballasting because their temperature coefficient of Vgs (or Rds or transconductance - I forget exactly which and it would take too long to find my old Siliconix book) enforces current sharing between cells; an area of the die which heats up has an increase in Rds lowering the current and power dissipation in that area.  The same behavior allows MOSFETs to share current when multiple parts are connected in parallel.

At higher voltages, the temperature coefficient reverses so areas that heat up draw more current and can experience thermal runaway.  This is very similar to what happens in bipolar transistors experiencing secondary breakdown which is ironic since one of the advertised advantages of MOSFETs is or was their lack of secondary breakdown behavior.

MOSFETs optimized for switching applications suffer from this to a greater extent and they are often or usually not even characterized for linear operation.  I was pleasantly surprised to see that the IRFS7530 datasheet includes this behavior in its safe operating area graph because most leave it out although the voltage at which this starts to occur is surprisingly low.

As far as rated power dissipation at a 25C case temperature, I think about this specification in the same way as third-order intercept point.  The number is unrealistic but useful for calculating the actual limit to power dissipation at different temperatures.

[T3sl4co1l]

This behavior is not widely advertised for obvious reasons.  Most datasheets show a straight line along the power limit of the safe operating area curve.

At low voltages, power MOSFETs are self ballasting because their temperature coefficient of Vgs (or Rds or transconductance - I forget exactly which and it would take too long to find my old Siliconix book) enforces current sharing between cells; an area of the die which heats up has an increase in Rds lowering the current and power dissipation in that area.  The same behavior allows MOSFETs to share current when multiple parts are connected in parallel.

Easy way to remember it: amplification and Vbe always have negative tempco, bulk silicon (as a resistor) always has positive.

So, MOSFETs operating saturated in the Rds(on) limited region, gain is minuscule so the tempco is essentially just the current flowing through bulk silicon.  Up in the linear range (out of [voltage] saturation), it's running gain, and the voltage drop in the silicon is still present, but because it's the CCS region, that internal voltage drop is taken up and there's very little positive tempco remaining, the negative is wholly dominant.

Diodes exhibit both junction and resistive drop; the resistive part becomes more prominent at higher currents, and so it shouldn't be surprising that all diodes have a crossover point where tempco actually becomes positive.  (It's usually at a high pulse current though.)

At higher voltages, the temperature coefficient reverses so areas that heat up draw more current and can experience thermal runaway.  This is very similar to what happens in bipolar transistors experiencing secondary breakdown which is ironic since one of the advertised advantages of MOSFETs is or was their lack of secondary breakdown behavior.

I believe the only reason MOSFETs were ever touted for that claim was because the power density of early designs (lateral and such) were so low -- now that VDMOS has finally been optimized to its fullest, and pushed to extreme Vdss ratings (up to 4kV in Si, I believe?), the power density is comparable, and 2nd breakdown is, well, it's not back, it never went away, you just couldn't reach that region of operation within quiescent ratings before, that's all!

MOSFETs optimized for switching applications suffer from this to a greater extent and they are often or usually not even characterized for linear operation.  I was pleasantly surprised to see that the IRFS7530 datasheet includes this behavior in its safe operating area graph because most leave it out although the voltage at which this starts to occur is surprisingly low.

Yeah, if you don't see DC SOA, and you need DC operation, keep looking.  It's possible they left it out due to laziness (I'm guessing it's slow to test that), but it's more likely it's simply no good there.

As far as rated power dissipation at a 25C case temperature, I think about this specification in the same way as third-order intercept point.  The number is unrealistic but useful for calculating the actual limit to power dissipation at different temperatures.

The number is absolutely real, it's not pulsed or anything (the 10us pulsed rating is in the 10s of kW, BTW).  It's just inapplicable under normal conditions, where you have a pile of stuff between "all surfaces of the transistor" and "cold things".

Tim

[David Hess]

At higher voltages, the temperature coefficient reverses so areas that heat up draw more current and can experience thermal runaway.  This is very similar to what happens in bipolar transistors experiencing secondary breakdown which is ironic since one of the advertised advantages of MOSFETs is or was their lack of secondary breakdown behavior.

I believe the only reason MOSFETs were ever touted for that claim was because the power density of early designs (lateral and such) were so low -- now that VDMOS has finally been optimized to its fullest, and pushed to extreme Vdss ratings (up to 4kV in Si, I believe?), the power density is comparable, and 2nd breakdown is, well, it's not back, it never went away, you just couldn't reach that region of operation within quiescent ratings before, that's all!

The old graphs I remember showed the zero temperature coefficient point significantly above that of the secondary breakdown region of bipolar transistors (about 30 volts) for vertically constructed MOSFETs but even then parts with a Vds significantly above that were available.  This was back in 1985.  Now that point is below that of bipolar transistors but still high enough for current sharing in switching applications and linear designs are a lot less common now.

It is too bad there is no electronic copy of this available.  I am up to two different dead tree editions at this point:

http://www.amazon.com/Mospower-Applications-Handbook-Rudy-Severns/dp/0930519000

[pstemari]

Well, I wound up ordering a couple IXTH40N50L2's from Digikey.

We'll see how those do. I'll probably wind up making a water-cooled heatsink if I need to push the power level. As it turns out I only need 30V@3A for the current application, not 30V@10A.

Seems like the TO-247 should be able to handle 90W easly.

[Mr.B]

Well, I wound up ordering a couple IXTH40N50L2's from Digikey.

I am using IXTH30N50L2 in my design.
I expect to be able to easily push them to 100W.

https://www.eevblog.com/forum/projects/home-brew-dc-load-design-review/msg571781/#msg571781